ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 135
ATTINY40-MMHR
Manufacturer Part Number
ATTINY40-MMHR
Description
MCU AVR 4KB FLASH 12MHZ 3X3 QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY40-MMHR.pdf
(216 pages)
Specifications of ATTINY40-MMHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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17.3.7
8263A–AVR–08/10
Clock and Clock Stretching
Figure 17-6. Master Read Transaction
Given that the slave acknowledges the address, the master can start receiving data from the
slave. There are no limitations to the number of data packets that can be transferred. The slave
transmits the data while the master signals ACK or NACK after each data byte. The master ter-
minates the transfer with a NACK before issuing a STOP condition.
Figure 17-7
and write transactions separated by a Repeated START conditions (Sr).
Figure 17-7. Combined Transaction
All devices connected to the bus are allowed to stretch the low period of the clock to slow down
the overall clock frequency or to insert wait states while processing data. A device that needs to
stretch the clock can do this by holding/forcing the SCL line low after it detects a low level on the
line.
Three types of clock stretching can be defined as shown in
Figure 17-8. Clock Stretching
If the device is in a sleep mode and a START condition is detected the clock is stretched during
the wake-up period for the device.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit
level. This allows the slave to run at a lower system clock frequency. However, the overall per-
formance of the bus will be reduced accordingly. Both the master and slave device can
randomly stretch the clock on a byte level basis before and after the ACK/NACK bit. This pro-
vides time to process incoming or prepare outgoing data, or performing other time critical tasks.
S
SDA
SCL
S
ADDRESS
Address Packet #1
illustrates a combined transaction. A combined transaction consists of several read
ADDRESS
Address Packet
S
R/W
Wakeup clock
stretching
A
Direction
bit 7
R
N Data Packets
DATA
A
bit 6
A/A
Transaction
DATA
Transaction
Data Packet
Periodic clock
stretching
Sr
ADDRESS
Address Packet #2
N data packets
A
Figure
bit 0
R/W
17-8.
A
DATA
Direction
ACK/NACK
M Data Packets
Random clock
DATA
stretching
A
A/A P
P
135
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