ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 89

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.7.3
12.7.4
12.7.5
12.8
8263A–AVR–08/10
Timer/Counter Timing Diagrams
Normal, 16-bit Mode
8-bit Input Capture Mode
16-bit Input Capture Mode
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur. As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
In 16-bit mode, see
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
bottom (0x0000). The Overflow Flag (TOV1) will be set in the same timer clock cycle as the
TCNT1H/L becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is
only set, not cleared. However, combined with the timer overflow interrupt that automatically
clears the TOV1 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime. The Output
Compare Unit can be used to generate interrupts at some given time.
The Timer/Counter1 can also be used in an 8-bit Input Capture mode, see
88
The Timer/Counter1 can also be used in a 16-bit Input Capture mode, see
88
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value.
Figure 12-5. Timer/Counter Timing Diagram, no Prescaling
Figure 12-6
TCNTn
(clk
TOVn
clk
clk
for bit settings. For full description, see the section
for bit settings. For full description, see the section
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
Figure 12-5
Table 12-3 on page
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
88, the counter (TCNT1H/L) is a incrementing until it
MAX
“Input Capture Unit” on page
“Input Capture Unit” on page
BOTTOM
T1
) is therefore shown as a
Table 12-3 on page
Table 12-3 on page
BOTTOM + 1
85.
85.
89