MC9S12H256VFVE Freescale Semiconductor, MC9S12H256VFVE Datasheet - Page 85

• Manufacturer Part Number: MC9S12H256VFVE
• Description: IC MCU 256K FLASH 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12H256VFVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 115
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC9S12H256 Device User Guide — V01.20
There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult
the MSCAN Block User Guide for information on each MSCAN.
Section 19 PWM Motor Control (MC) Block Description
Consult the MC_10B12C Block User Guide for information about the PWM Motor Control module.
Section 20 Port Integration Module (PIM) Block Description
Consult the PIM_9H256 Block User Guide for information about the Port Integration Module.
Section 21 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
21.1 Device-specific information
21.1.1 VREGEN
There is no VREGEN pin implemented on this device.
21.1.2 Modes of Operation
21.1.2.1 Run Mode
VREG enters run mode whenever the CPU is neither in Stop nor in Pseudo Stop mode. Both regulating
loops operate in Run mode with full performance.
21.1.2.2 Standby Mode
VREG enters Standby mode when the CPU operates either in Stop or in Pseudo Stop mode. The supply of
the core logic as well as the oscillators are derived from two voltage clamps. Standby mode minimizes
quiescent current drawn by the voltage regulator block.
21.1.2.3 Shutdown Mode
VREG Shutdown mode is not available on MC9S12H family devices.
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