MC9S12H256VFVE Freescale Semiconductor, MC9S12H256VFVE Datasheet - Page 71

• Manufacturer Part Number: MC9S12H256VFVE
• Description: IC MCU 256K FLASH 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12H256VFVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 115
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12H256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
There are two basic types of operating modes:
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
MODC
0
0
0
0
1
1
1
1
MODB
0
0
1
1
0
0
1
1
MODA
0
1
0
1
0
1
0
1
Table 4-1 Mode Selection
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide) (Freescale Use Only), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral (Freescale Use Only); BDM allowed but bus operations
would cause bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
Mode Description
MC9S12H256 Device User Guide — V01.20
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