C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 46

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

C8051F70x/71x
46
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
C2
X1
E
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
to assure good solder paste release.
pad.
Body Components.
Figure 8.2. QFN-24 Recommended PCB Land Pattern
Table 8.2. QFN-24 PCB Land Pattern Dimensions
3.90
3.90
0.20
Min
0.50 BSC
0.30
Max
4.00
4.00
Rev. 1.0
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80