C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 155

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

C8051F70x/71x
23. EEPROM
C8051F700/1/4/5/8/9 and C8051F712/3 devices have hardware which emulates 32 bytes of non-volatile,
byte-programmable EEPROM data space. The module mirrors each non-volatile byte through 32 bytes of
volatile data space. This data space can be accessed indirectly through EEADDR and EEDATA. Users can
copy the complete 32-byte image between EEPROM space and volatile space using controls in the
EECNTL SFR.
EEKEY
EEADDR
EEDATA
EECNTL
32 Bytes
32 Bytes RAM
EEPROM
EEPROM Control
Logic
Figure 23.1. EEPROM Block Diagram
23.1. RAM Reads and Writes
In order to perform EEPROM reads and writes, the EEPROM control logic must be enabled by setting
EEEN (EECNTL.7).
32 bytes of RAM can be accessed indirectly through EEADDR and EEDATA. To write to a byte of RAM,
write address of byte to EEADDR and then write the value to be written to EEDATA. To read a byte from
RAM, write address of byte to be read to EEADDR. The value stored at that address can then be read from
EEDATA.
23.2. Auto Increment
When AUTOINC (EECNTL.0) is set, EEADDR will increment by one after each write to EEDATA and each
read from EEDATA. When Auto Increment is enabled and EEADDR reaches the top address of dedicated
RAM space, the next write to or read from EEDATA will cause EEADDR to wrap along the address bound-
ary, which will set the address to 0.
23.3. Interfacing with the EEPROM
The EEPROM is accessed through the dedicated 32 bytes of RAM. Writes to EEPROM are allowed only
after writes have been enabled (see “23.4. EEPROM Security” ). The contents of the EEPROM can be
uploaded to the RAM by setting EEREAD (EECNTL.2). Contents of RAM can be downloaded to EEPROM
by setting EEWRT (EENTL.1).
Note: A minimum SYSCLK frequency is required for writing EEPROM memory, as detailed in Section
Table 9.9. EEPROM Electrical Characteristics
52
“
” on page
.
Rev. 1.0
155