P89LPC931FDH,112 NXP Semiconductors, P89LPC931FDH,112 Datasheet - Page 31

• Manufacturer Part Number: P89LPC931FDH,112
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC931FDH,112

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 45 C
• For Use With: 622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1284-5; 935273877112; P89LPC931FDH; P89LPC931FDH,129; P89LPC931FDH-S

Philips Semiconductors
9397 750 14472
Product data
8.19 Serial Peripheral Interface (SPI)
LPC930/931 provides another high-speed serial communication interface - the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported
in Master or 3.0 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write
Collision Flag Protection.
Fig 8. I
P1.3/SDA
P1.2/SCL
2
C-bus serial interface block diagram.
Rev. 05 — 15 December 2004
OUTPUT
OUTPUT
FILTER
STAGE
FILTER
STAGE
INPUT
INPUT
P1.3
P1.2
STATUS BUS
OVERFLOW
TIMER 1
I2SCLH
I2SCLL
I2CON
8-bit microcontrollers with two-clock 80C51 core
I2STAT
ARBITRATION &
BIT COUNTER /
SERIAL CLOCK
SYNC LOGIC
GENERATOR
SCL DUTY CYCLE REGISTERS
ADDRESS REGISTER
CONTROL REGISTERS &
SHIFT REGISTER
DECODER
COMPARATOR
STATUS
STATUS REGISTER
P89LPC930/931
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8
CONTROL
TIMING
LOGIC
&
I2DAT
8
8
8
ACK
I2ADR
CCLK
INTERRUPT
002aaa421
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