P89LPC931FDH,112 NXP Semiconductors, P89LPC931FDH,112 Datasheet - Page 20

IC 80C51 MCU FLASH 8K 28-TSSOP

P89LPC931FDH,112

Manufacturer Part Number
P89LPC931FDH,112
Description
IC 80C51 MCU FLASH 8K 28-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC931FDH,112

Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
P89LPC9x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
26
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 45 C
For Use With
622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
568-1284-5
935273877112
P89LPC931FDH
P89LPC931FDH,129
P89LPC931FDH-S
Philips Semiconductors
9397 750 14472
Product data
8.10.1 External interrupt inputs
8.10 Interrupts
The P89LPC930/931 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The
P89LPC930/931 supports 13 interrupt sources: external interrupts 0 and 1, timers 0
and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,
watchdog/real-time clock, I
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
The P89LPC930/931 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC930/931 is put into Power-down
or Idle mode, the interrupt will cause the processor to wake-up and resume operation.
Refer to
Section 8.13 “Power reduction modes”
Rev. 05 — 15 December 2004
2
C, keyboard, and comparators 1 and 2, and SPI.
8-bit microcontrollers with two-clock 80C51 core
for details.
P89LPC930/931
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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