PIC12CE519/JW Microchip Technology, PIC12CE519/JW Datasheet - Page 492
![IC MCU EPROM 1KX12 W/EE 8CDIP](/photos/12/23/122362/pic12ce519_jw_sml.jpg)
PIC12CE519/JW
Manufacturer Part Number
PIC12CE519/JW
Description
IC MCU EPROM 1KX12 W/EE 8CDIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE519/JW
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
EPROM, UV
Eeprom Size
16 x 8
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-CDIP (0.300", 7.62mm) Window
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12CE519/JW
Manufacturer:
MICROCH
Quantity:
20 000
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 492 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
26.4.2
DS31026A-page 26-8
Note 1: XT, HS or LP oscillator mode assumed.
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT
2: T
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
INT pin
OSC1
PC
(4)
continue in-line.
Wake-up Using Interrupts
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
When interrupts are globally disabled (GIE cleared) and any interrupt source has both its inter-
rupt enable bit and interrupt flag set, one of the following events will occur:
• If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will
Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for
flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP
instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as
an NOP.
To ensure that the WDT is clear, a CLRWDT instruction should be executed before a SLEEP instruc-
tion.
Figure 26-2: Wake-up from Sleep Through Interrupt
OSC
complete as an NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO
bit will not be set and PD bit will not be cleared.
immediately wake-up from sleep. The SLEEP instruction will be completely executed before
the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
(drawing not to scale) This delay will not be there for RC osc mode.
Q1 Q2 Q3 Q4
Inst(PC + 1)
SLEEP
PC+1
Q1
Processor in
SLEEP
PC+2
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
PC+2
Interrupt Latency
Dummy cycle
PC + 2
(2)
Q1 Q2 Q3 Q4
Inst(0004h)
Dummy cycle
1997 Microchip Technology Inc.
0004h
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h
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