PIC12CE519/JW Microchip Technology, PIC12CE519/JW Datasheet - Page 450
![IC MCU EPROM 1KX12 W/EE 8CDIP](/photos/12/23/122362/pic12ce519_jw_sml.jpg)
PIC12CE519/JW
Manufacturer Part Number
PIC12CE519/JW
Description
IC MCU EPROM 1KX12 W/EE 8CDIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE519/JW
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
EPROM, UV
Eeprom Size
16 x 8
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-CDIP (0.300", 7.62mm) Window
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12CE519/JW
Manufacturer:
MICROCH
Quantity:
20 000
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 450 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
24.3.1
DS31024A-page 24-8
Slope A/D Timer (ADTMR)
The Slope A/D timer (ADTMR) is comprised of a 16-bit timer (ADTMRH:ADTMRL), which is
incremented every oscillator cycle. The ADTMR registers are cleared by a power-on reset; oth-
erwise the software must initialize it after each conversion. A separate 16-bit capture register
(ADCAPH:ADCAPL) is used to capture the ADTMR count if a Slope A/D capture event occurs
(see below). Both the Slope A/D timer and capture registers are readable and writable. The 16-bit
timer is a read/write register and is cleared on any device reset.
During a conversion one or both of the following events will occur:
• capture event
• timer overflow
In a capture event, the comparator trips when the slope voltage on the CDAC output exceeds the
input voltage from the selected Slope A/D channel, causing the comparator output to transition
from high to low. This causes a transfer of the current timer count to the capture register and sets
the ADCIF flag bit.
An interrupt will be generated if the ADCIE bit is set (interrupt enabled). In addition, GIE and PIE
bits must be set. Software is responsible for clearing the ADCIF flag bit prior to the next conver-
sion cycle. This interrupt can only occur once per conversion cycle.
In a timer overflow condition, the timer rolls over from FFFFh to 0000h, and a capture overflow
flag (OVFIF) is asserted. The timer continues to increment following a timer overflow. An interrupt
can be generated if bit OVFIE is set (interrupt enabled). In addition, the GIE and PIE bits must
be set. Software is responsible for clearing the OVFIF flag bit prior to the next conversion cycle.
Figure 24-2: Example Slope A/D Conversion Cycle
Note 1: Reading or writing the ADTMR register during an Slope A/D conversion cycle can
Note 2: The correct sequence for writing the ADTMR register is HI byte followed by LO byte.
produce unpredictable results and is not recommended.
Reversing this order will prevent the Slope A/D timer from running.
CAPTURE
CLK
ADRST
ADCON0<1>
CDAC
ADCIF
Capture
Register
ADTMR
COUNT
(must be cleared by software)
XX
ADTMR INCREMENTS
XX+1 XX+2 XX+3
XX
XX+8 XX+9
1997 Microchip Technology Inc.
COMPARE
XX+8
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