PIC18LF4685-I/P Microchip Technology, PIC18LF4685-I/P Datasheet - Page 90
![IC PIC MCU FLASH 48KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4685-I/P
Manufacturer Part Number
PIC18LF4685-I/P
Description
IC PIC MCU FLASH 48KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XT0.pdf
(484 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2682-ISP.pdf
(6 pages)
5.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF4685-I/P
Core Size
8-Bit
Program Memory Size
96KB (48K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
44
Interface Type
CAN/I2C/SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
4
Core
PIC
Processor Series
PIC18LF
Maximum Clock Frequency
40 MHz
Data Ram Size
3.25 KB
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
11
Height
4.95 mm
Length
53.21 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
14.73 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4685-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF4685-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XT0 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- PIC18F2682-ISP PDF datasheet #5
- Current page: 90 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
5.4
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.1
Many PIC18 control instructions do not need any
argument at all. They either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW which, respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
DS39761C-page 90
Note:
Data Addressing Modes
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data
Memory and the Extended Instruction
Set” for more information.
INHERENT AND LITERAL
ADDRESSING
DIRECT ADDRESSING
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In those cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction.
Their destination is either the target register being
operated on or the W register.
5.4.3
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5:
NEXT
CONTINUE
LFSR
CLRF
BTFSS FSR0H, 1
BRA
INDIRECT ADDRESSING
FSR0, 100h
POSTINC0
NEXT
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
© 2009 Microchip Technology Inc.
;
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
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