PIC18LF4685-I/P Microchip Technology, PIC18LF4685-I/P Datasheet - Page 407
![IC PIC MCU FLASH 48KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4685-I/P
Manufacturer Part Number
PIC18LF4685-I/P
Description
IC PIC MCU FLASH 48KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XT0.pdf
(484 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2682-ISP.pdf
(6 pages)
5.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF4685-I/P
Core Size
8-Bit
Program Memory Size
96KB (48K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
44
Interface Type
CAN/I2C/SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
4
Core
PIC
Processor Series
PIC18LF
Maximum Clock Frequency
40 MHz
Data Ram Size
3.25 KB
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
11
Height
4.95 mm
Length
53.21 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
14.73 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4685-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF4685-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XT0 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- PIC18F2682-ISP PDF datasheet #5
- Current page: 407 of 484
- Download datasheet (9Mb)
25.2
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F2682/2685/4682/4685 devices
also provide an optional extension to the core CPU
functionality. The added features include eight
additional instructions that augment indirect and
indexed addressing operations and the implementation
of Indexed Literal Offset Addressing mode for many of
the standard PIC18 instructions.
The additional features are disabled by default. To
enable them, users must set the XINST Configuration
bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• Dynamic allocation and deallocation of software
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
TABLE 25-3:
© 2009 Microchip Technology Inc.
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
stack space when entering and leaving
subroutines
stack
Mnemonic,
Operands
Extended Instruction Set
f, k
k
z
z
k
f, k
k
s
s
, f
, z
d
EXTENSIONS TO THE PIC18 INSTRUCTION SET
d
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move z
Move z
Store literal at FSR2,
Subtract literal from FSR
Subtract literal from FSR2 and
decrement FSR2
return
f
z
d
s
s
d
(destination) 2nd word
(source) to
(source) to
(destination) 2nd word
Description
1st word
1st word
PIC18F2682/2685/4682/4685
Cycles
1
2
2
2
2
1
1
2
A summary of the instructions in the extended instruc-
tion set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 25-1 apply
to both the standard and extended PIC18 instruction
sets.
25.2.1
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. MPASM™ Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in bit-
oriented and byte-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 25.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
Note:
Note:
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
MSb
16-Bit Instruction Word
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
EXTENDED INSTRUCTION SYNTAX
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional arguments
are denoted by braces (“{ }”).
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
ffkk
11kk
0001
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
LSb
DS39761C-page 407
Affected
Status
None
None
None
None
None
None
None
None
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