PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 89

IC MCU CAN FLASH 8K LP 28DIP

PIC18LF248-I/SP

Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF248-I/SP

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
REGISTER 8-9:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
bit 7
IRXIE: Invalid CAN Message Received Interrupt Enable bit
1 = Enables the invalid CAN message received interrupt
0 = Disables the invalid CAN message received interrupt
WAKIE: Bus Activity Wake-up Interrupt Enable bit
1 = Enables the bus activity wake-up interrupt
0 = Disables the bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1 = Enables the CAN bus error interrupt
0 = Disables the CAN bus error interrupt
TXB2IE: Transmit Buffer 2 Interrupt Enable bit
1 = Enables the Transmit Buffer 2 interrupt
0 = Disables the Transmit Buffer 2 interrupt
TXB1IE: Transmit Buffer 1 Interrupt Enable bit
1 = Enables the Transmit Buffer 1 interrupt
0 = Disables the Transmit Buffer 1 interrupt
TXB0IE: Transmit Buffer 0 Interrupt Enable bit
1 = Enables the Transmit Buffer 0 interrupt
0 = Disables the Transmit Buffer 0 interrupt
RXB1IE: Receive Buffer 1 Interrupt Enable bit
1 = Enables the Receive Buffer 1 interrupt
0 = Disables the Receive Buffer 1 interrupt
RXB0IE: Receive Buffer 0 Interrupt Enable bit
1 = Enables the Receive Buffer 0 interrupt
0 = Disables the Receive Buffer 0 interrupt
Legend:
R = Readable bit
-n = Value at POR
R/W-1
IRXIE
WAKIE
R/W-1
ERRIE
R/W-1
W = Writable bit
‘1’ = Bit is set
TXB2IE
R/W-1
TXB1IE
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXB0IE
R/W-1
PIC18FXX8
x = Bit is unknown
RXB1IE
R/W-1
DS41159E-page 87
RXB0IE
R/W-1
bit 0

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