PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 153
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PIC18LF248-I/SP
Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 153 of 402
- Download datasheet (7Mb)
17.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISA
SSPBUF
SSPCON1
SSPSTAT
Legend:
Note 1:
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
WCOL
Bit 7
SMP
—
REGISTERS ASSOCIATED WITH SPI™ OPERATION
(1)
(1)
(1)
TRISA6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
TRISA5
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
TRISA4
INT0IE
Bit 4
TXIF
TXIE
TXIP
CKP
P
TRISA3
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also an SMP bit which controls when the data
is sampled.
Standard SPI Mode
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISA2
SSPM2
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
BUS MODE COMPATIBILITY
TMR2IE
TMR2IP
TMR2IF
TRISA1
SSPM1
INT0IF
Bit 1
UA
SPI™ BUS MODES
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
TMR1IF
TRISA0
SSPM0
RBIF
Bit 0
BF
PIC18FXX8
CKP
Control Bits State
0
0
1
1
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
-111 1111 -111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
POR, BOR
Value on
DS41159E-page 151
CKE
Value on
all other
Resets
1
0
1
0
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