PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 274
![IC MCU CAN FLASH 8K LP 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF248-I/SP
Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 274 of 402
- Download datasheet (7Mb)
24.2
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up
(Watchdog Timer wake-up). The TO bit in the RCON
register will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software
execution may not disable this function. When the
WDTEN configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
REGISTER 24-13: WDTCON: WATCHDOG TIMER CONTROL REGISTER
DS41159E-page 272
PIC18FXX8
Watchdog Timer (WDT)
and
bit 7-1
bit 0
continue
bit 7
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
U-0
—
with
normal
U-0
—
operation
U-0
—
U-0
—
The WDT time-out period values may be found in
Section 27.0 “Electrical Characteristics” under
parameter #31. Values for the WDT postscaler may be
assigned using the configuration bits.
24.2.1
Register 24-13 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
W = Writable bit
-n = Value at POR
Note:
Note:
U-0
—
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT and prevent it from timing out
and generating a device Reset condition.
When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared but the
postscaler assignment is not changed.
CONTROL REGISTER
U-0
—
© 2006 Microchip Technology Inc.
U-0
—
SWDTEN
R/W-0
bit 0
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