PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 245

• Manufacturer Part Number: PIC18LF248-I/SP
• Description: IC MCU CAN FLASH 8K LP 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF248-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(V
V
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
FIGURE 20-1:
© 2006 Microchip Technology Inc.
REF
DD
+ pin and RA2/AN2/V
and V
Note 1: Channels AN5 through AN7 are not available on PIC18F2X8 devices.
SS
2: All I/O pins have diode protection to V
) or the voltage level on the RA3/AN3/
Converter
10-bit
A/D
Reference
voltage
A/D BLOCK DIAGRAM
REF
- pin.
V
V
REF
REF
-
+
(Input Voltage)
V
AIN
PCFG0
DD
and V
V
DD
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a
voltage reference) or as a digital I/O.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0<2>) is cleared
and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 20-1.
SS
.
V
SS
CHS2:CHS0
111
110
101
100
011
010
001
000
PIC18FXX8
DS41159E-page 243
AN7
AN2
AN1
AN0
AN6
AN5
AN4
AN3
(1)
(1)
(1)