MC9S12XDT512MAA Freescale Semiconductor, MC9S12XDT512MAA Datasheet - Page 73

• Manufacturer Part Number: MC9S12XDT512MAA
• Description: IC MCU 512K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT512MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Vector base + $CC
Vector base + $EC
Vector base + $DA
Vector base + $CE
Vector base + $CA
Vector base + $F8
Vector base + $E2
Vector base+ $DC
Vector base + $D8
Vector base + $D4
Vector base + $D2
Vector base + $D2
Vector base + $D0
Vector base + $C8
Vector base + $C6
Vector base + $C4
Vector base + $C2
Vector base + $C0
Vector base+ $EE
Vector base+ $EA
Vector base+ $DE
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base+ $E0
Vector base+ $D6
Vector Address
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
$FFFE
$FFFC
$FFFA
1
Channel ID
XGATE
$6D
$6C
$6F
$6E
$6B
$6A
$78
$77
$76
$75
$74
$73
$72
$71
$70
$69
$68
$67
$66
$65
$64
$63
$62
$60
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Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
2
MC9S12XDP512 Data Sheet, Rev. 2.21
System reset or illegal access reset
Enhanced capture timer channel 0
Enhanced capture timer channel 1
Enhanced capture timer channel 2
Enhanced capture timer channel 3
Enhanced capture timer channel 4
Enhanced capture timer channel 5
Enhanced capture timer channel 6
Enhanced capture timer channel 7
Enhanced capture timer overflow
Modulus down counter underflow
Unimplemented instruction trap
Pulse accumulator input edge
Pulse accumulator A overflow
Pulse accumulator B overflow
CRG self-clock mode
COP watchdog reset
Clock monitor reset
Real time interrupt
Interrupt Source
CRG PLL lock
IIC0 bus
Port H
Port J
XIRQ
ATD0
ATD1
SPI0
SCI0
SCI1
SWI
IRQ
Reserved
Reserved
Chapter 1 Device Overview MC9S12XD-Family
Mask
None
None
None
None
None
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
SPI0CR1 (SPIE, SPTIE)
PLLCTL (CME, SCME)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
PIEH (PIEH7-PIEH0)
ATD0CTL2 (ASCIE)
ATD1CTL2 (ASCIE)
PIEJ (PIEJ7-PIEJ0)
CRGINT(LOCKIE)
CRGINT (SCMIE)
IRQCR (IRQEN)
COP rate select
CRGINT (RTIE)
PACTL (PAOVI)
PBCTL(PBOVI)
MCCTL(MCZI)
TSRC2 (TOF)
Local Enable
IBCR0 (IBIE)
PACTL (PAI)
SCI0CR2
SCI1CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
None
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