MC9S12XDT512MAA Freescale Semiconductor, MC9S12XDT512MAA Datasheet - Page 1194

• Manufacturer Part Number: MC9S12XDT512MAA
• Description: IC MCU 512K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT512MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
29.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
29.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
1196
RESERVED1
RESERVED2
RESERVED3
RESERVED4
FDIV[5:0]
PRDIV8
FDIVLD
Register
Reset
Field
Name
5:0
7
6
W
R
FDIVLD
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8
0 The oscillator clock is directly fed into the clock divider
1 The oscillator clock is divided by 8 before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to
FCLKDIV Register”
Flash Clock Divider Register (FCLKDIV)
Flash Security Register (FSEC)
0
7
W
W
W
W
R
R
R
R
Bit 7
= Unimplemented or Reserved
0
0
0
0
PRDIV8
Figure 29-3. FTX128K1 Register Summary (continued)
0
6
Figure 29-4. Flash Clock Divider Register (FCLKDIV)
for more information.
.
6
0
0
0
0
Table 29-2. FCLKDIV Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
FDIV5
0
5
5
0
0
0
0
FDIV4
0
4
Description
4
0
0
0
0
.
FDIV3
0
3
3
0
0
0
0
FDIV2
0
2
2
0
0
0
0
Section 29.4.1.1, “Writing the
Freescale Semiconductor
FDIV1
0
1
1
0
0
0
0
FDIV0
Bit 0
0
0
0
0
0
0