MC9S12XDT512MAA Freescale Semiconductor, MC9S12XDT512MAA Datasheet - Page 429

• Manufacturer Part Number: MC9S12XDT512MAA
• Description: IC MCU 512K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT512MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.2.4
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
1
Freescale Semiconductor
TSEG2[2:0]
TSEG1[3:0]
In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
SAMP
Field
6:4
3:0
7
Reset:
W
R
BRP5
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
MSCAN Bus Timing Register 1 (CANBTR1)
0
0
0
0
1
:
SAMP
0
7
10-7.
10-8.
BRP4
0
0
0
0
1
:
Figure 10-7. MSCAN Bus Timing Register 1 (CANBTR1)
TSEG22
Table 10-6. CANBTR1 Register Field Descriptions
BRP3
0
6
0
0
0
0
1
:
Table 10-5. Baud Rate Prescaler
1
Figure
Figure
.
MC9S12XDP512 Data Sheet, Rev. 2.21
BRP2
TSEG21
0
0
0
0
1
:
10-44). Time segment 2 (TSEG2) values are programmable as shown in
10-44). Time segment 1 (TSEG1) values are programmable as shown in
0
5
BRP1
0
0
1
1
1
:
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
TSEG20
0
4
BRP0
Description
0
1
0
1
1
:
TSEG13
3
0
Prescaler value (P)
TSEG12
64
0
2
1
2
3
4
:
TSEG11
0
1
TSEG10
0
0
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