MC912DG128ACPVER Freescale Semiconductor, MC912DG128ACPVER Datasheet - Page 183
![IC MCU 16BIT 8K FLASH 112-LQFP](/photos/12/21/122171/mc912dg128acpver_sml.jpg)
MC912DG128ACPVER
Manufacturer Part Number
MC912DG128ACPVER
Description
IC MCU 16BIT 8K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DG128ACPVER
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 8 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC912DG128ACPVERTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC68HC912DT128A — Rev 4.0
MOTOROLA
MCLK
XCLK
÷
÷
1, 2, 3, 4, 5, 6,...,8190, 8191
1, 2, 3, 4, 5, 6,...,8190, 8191
REGISTER: RTICTL
BIT:RTBYP
MODULUS DIVIDER:
MODULUS DIVIDER:
÷
SC0BD
SC1BD
2048
Figure 12-7. Clock Chain for SCI0, SCI1, RTI, COP
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
the transition, the clock select output will be held low and all CPU activity
will cease until the transition is complete.
The Module Clock Select bit MCS determines the clock used by the ECT
module and the baud rate generators of the SCIs. In limp-home mode,
the output of MCS is forced to 0, but the MCS bit reads the latched value.
It allows normal operation of the serial and timer subsystems at a fixed
reference frequency while allowing the CPU to operate at a higher,
variable frequency.
Freescale Semiconductor, Inc.
For More Information On This Product,
÷
÷
16
16
÷
Go to: www.freescale.com
4
BAUD RATE (16x)
BAUD RATE (16x)
BAUD RATE (1x)
BAUD RATE (1x)
TRANSMIT
TRANSMIT
RECEIVE
RECEIVE
Clock Functions
SCI0
SCI0
SCI1
SCI1
BITS: RTR2, RTR1, RTR0
REGISTER: RTICTL
÷
÷
÷
÷
÷
÷
2
2
2
2
2
2
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
0:0:0
TO RTI
BITS: CR2, CR1, CR0
REGISTER: COPCTL
÷
÷
÷
÷
÷
÷
4
4
4
4
2
2
Clock Divider Chains
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Clock Functions
0:0:0
Technical Data
TO COP
183
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