MC912DG128ACPVER Freescale Semiconductor, MC912DG128ACPVER Datasheet - Page 108
![IC MCU 16BIT 8K FLASH 112-LQFP](/photos/12/21/122171/mc912dg128acpver_sml.jpg)
MC912DG128ACPVER
Manufacturer Part Number
MC912DG128ACPVER
Description
IC MCU 16BIT 8K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DG128ACPVER
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 8 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC912DG128ACPVERTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PEAR — Port E Assignment Register
Bus Control and Input/Output
Technical Data
108
RESET:
RESET:
RESET:
RESET:
RESET:
NDBE
BIT 7
0
0
1
1
0
CGMTE
6
0
0
1
0
0
Port E serves as general purpose I/O lines or as system and bus
control signals. The PEAR register is used to choose between the
general-purpose I/O functions and the alternate bus control functions.
When an alternate control function is selected, the associated DDRE
bits are overridden.
The reset condition of this register depends on the mode of operation
because bus control signals are needed immediately after reset in
some modes.
In normal single-chip mode, no external bus control signals are
needed so all of port E is configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external
memory. The DBE and E clock are required for de-multiplexing
address and data but LSTRB and R/W are only needed by the system
when there are external writable resources. Therefore in normal
expanded modes, the DBE and the E clock are configured for their
alternate bus control functions and the other bits of port E are
configured for general-purpose I/O. If the normal expanded system
needs any other bus control signals, PEAR would need to be written
before any access that needed the additional signals.
In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and
R/W are configured as bus-control signals.
In special single chip modes, DBE, IPIPE1, IPIPE0, E, LSTRB, R/W,
and CALE are configured as bus-control signals.
Freescale Semiconductor, Inc.
For More Information On This Product,
PIPOE
5
0
1
0
0
1
Bus Control and Input/Output
Go to: www.freescale.com
NECLK
4
0
0
1
1
0
LSTRE
3
0
1
0
0
1
RDWE
2
0
1
0
0
1
MC68HC912DT128A — Rev 4.0
CALE
1
0
0
0
0
0
DBENE
BIT 0
0
0
0
0
0
MOTOROLA
Special Ex-
Normal sin-
Special sin-
Normal Ex-
Peripheral
gle chip
gle chip
panded
panded
$000A
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