MC912DG128ACPVER Freescale Semiconductor, MC912DG128ACPVER Datasheet - Page 145
![IC MCU 16BIT 8K FLASH 112-LQFP](/photos/12/21/122171/mc912dg128acpver_sml.jpg)
MC912DG128ACPVER
Manufacturer Part Number
MC912DG128ACPVER
Description
IC MCU 16BIT 8K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DG128ACPVER
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 8 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC912DG128ACPVERTR
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
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10.8.4 Clock Monitor Reset
10.9 Effects of Reset
10.9.1 Operating Mode and Memory Map
10.9.2 Clock and Watchdog Control Logic
MC68HC912DT128A — Rev 4.0
MOTOROLA
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The SMODN,
MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
The COP watchdog system is enabled, with the CR[2:0] bits set for the
longest duration time-out. The clock monitor is disabled. The RTIF flag
is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is
used. The DLY control bit is set to specify an oscillator start-up delay
upon recovery from STOP mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Resets and Interrupts
Resets and Interrupts
Effects of Reset
Technical Data
145
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