C8051F060-GQ Silicon Laboratories Inc, C8051F060-GQ Datasheet - Page 140

• Manufacturer Part Number: C8051F060-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F060-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1213

C8051F060/1/2/3/4/5/6/7
140
Bits7-0:
Bits7-0:
R/W
R/W
Bit7
Bit7
SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in
a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR-
LAST is the third entry. The SFR stack bytes may be used to alter the context in the SFR
Page Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from
interrupt cause push and pop the SFR Page Stack.
Write: Sets the SFR Page contained in the second byte of the SFR Stack. This will cause
the SFRPAGE SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the second byte of the SFR stack.
This is the value that will go to the SFR Page register upon a return from interrupt.
SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in
a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR-
LAST is the third entry. The SFR stack bytes may be used to alter the context in the SFR
Page Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from
interrupt cause push and pop the SFR Page Stack.
Write:
Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to
have this SFR page value upon a return from interrupt.
Read:
Returns the value of the SFR page contained in the last entry of the SFR stack.
R/W
R/W
Bit6
Bit6
R/W
R/W
Bit5
Bit5
Figure 13.11. SFRNEXT: SFR Next Register
Figure 13.12. SFRLAST: SFR Last Register
R/W
R/W
Bit4
Bit4
Rev. 1.2
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
0x86
All Pages
0x85
All Pages
Reset Value
Reset Value
00000000
00000000