MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 675

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

In
A.6.2
In
Freescale Semiconductor
Num
10
11
12
13
Table A-21
Figure A-8
1
1
2
3
4
5
6
9
(CPOL = 1)
(CPOL = 0)
(OUTPUT)
NOTE: Not defined!
(INPUT)
(INPUT)
(INPUT)
(INPUT)
MOSI
MISO
SCK
SCK
C
D
D
D
D
D
D
D
D
D
D
P
P
SS
Slave Mode
10
7
the timing diagram for slave mode with transmission format CPHA=0 is depicted.
the timing characteristics for master mode are listed.
SCK Frequency
SCK Period
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
note
see
2
5
Characteristic
MSB IN
Table A-21. SPI Master Mode Timing Characteristics
SLAVE MSB
6
4
Figure A-8. SPI Slave Timing (CPHA=0)
MC9S12C-Family / MC9S12GC-Family
1
4
BIT 6 . . . 1
BIT 6 . . . 1
9
Rev 01.24
12
12
Symbol
t
t
t
f
t
wsck
t
lead
t
vsck
t
t
t
sck
sck
t
vss
t
lag
su
ho
rfo
hi
rfi
11
1/2048
SLAVE LSB OUT
Min
LSB IN
20
—
—
—
—
—
—
—
2
8
8
13
13
11
3
Appendix A Electrical Characteristics
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
NOTE
SEE
2048
Max
1/2
30
15
—
—
—
—
—
—
8
8
8
Unit
f
t
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck
sck
675