HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 91

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4.1
4.1.2
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
4.1.3
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
ROM space
RAM space
I/O register with 8-bit data bus
width
I/O register with 16-bit data
bus width
Bit
7
6
5 to 0 —
Bit Name
ABIF
ABIE
Address Break Status Register (ABRKSR)
Break Address Registers (BARH, BARL)
Break Data Registers (BDRH, BDRL)
Access and Data Bus Used
Initial Value R/W
0
0
All 1
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
R/W
R/W
—
Word Access
Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
Lower 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
—
Rev. 5.00, 03/04, page 63 of 388
Byte Access
Upper 8 bits
Upper 8 bits
Upper 8 bits
—