C8051F310-GQ Silicon Laboratories Inc, C8051F310-GQ Datasheet - Page 98

• Manufacturer Part Number: C8051F310-GQ
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F310-GQ

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: 8051
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Digital Ic Case: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1445 - ADAPTER PROGRAM TOOLSTICK F310336-1329 - KIT REF DESIGN SENSORLESS BLDC336-1253 - DEV KIT FOR C8051F310/F311
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1252

C8051F310/1/2/3/4/5
9.1.
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
ramp time increases (V
the power-on and V
delay (T
Note: The maximum V
reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
98
RST
. An additional delay occurs before the device is released from reset; the delay decreases as the V
Power-On Reset
PORDelay
DD
) is typically less than 0.3 ms.
Logic HIGH
Logic LOW
reaches the V
Figure 9.2. Power-On and V
DD
2.70
2.55
2.0
1.0
DD
DD
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
ramp time is 1 ms; slower ramp times may cause the device to be released from
ramp time is defined as how fast V
/RST
RST
V
RST
level.
Power-On
Reset
T
PORDelay
Rev. 1.5
DD
Monitor Reset Timing
DD
ramps from 0 V to V
Monitor
Reset
VDD
DD
monitor is disabled following a
RST
VDD
). Figure 9.2. plots
DD
t
settles above
DD