C8051F310-GQ Silicon Laboratories Inc, C8051F310-GQ Datasheet - Page 119

• Manufacturer Part Number: C8051F310-GQ
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F310-GQ

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: 8051
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Digital Ic Case: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1445 - ADAPTER PROGRAM TOOLSTICK F310336-1329 - KIT REF DESIGN SENSORLESS BLDC336-1253 - DEV KIT FOR C8051F310/F311
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1252

13. Port Input/Output
Digital and analog resources are available through 29 I/O pins (C8051F310/2/4) or 25 I/O pins
(C8051F311/3/5). Port pins are organized as three byte-wide Ports and one 5-bit (C8051F310/2/4) or 1-bit
(C8051F311/3/5) Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog
input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 13.3.
The designer has complete control over which functions are assigned, limited only by the number of phys-
ical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. The state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the
Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 13.3 and Figure 13.4). The registers XBR0 and XBR1, defined in SFR Definition 13.1 and SFR
Definition 13.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 13.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Com-
plete Electrical Specifications for Port I/O are given in Table 13.1 on page 133.
Highest
Lowest
Priority
Priority
SYSCLK
Outputs
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
Figure 13.1. Port I/O Functional Block Diagram
PCA
CP0
CP1
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.3)
(P2.4-P2.7)
(P3.0-P3.4)
2
4
2
2
2
6
2
8
8
4
4
5
Rev. 1.5
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
4
C8051F310/1/2/3/4/5
4
8
8
PnMDIN Registers
8
5
PnMDOUT,
Note: P3.1-P3.4 only available
Cells
Cells
Cells
Cells
I/O
I/O
I/O
I/O
P0
P1
P2
P3
on the C8051F310/2/4
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
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