C8051F310-GQ Silicon Laboratories Inc, C8051F310-GQ Datasheet
C8051F310-GQ
Specifications of C8051F310-GQ
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C8051F310-GQ Summary of contents
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... MIPS throughput with 25 MHz clock - Expanded interrupt handler DD Memory - 1280 bytes internal data RAM (1024 + 256 (C8051F310/ (C8051F312/3/4/5) Flash; In-system programmable in 512-byte sectors Digital Peripherals - 29/25 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced UART, SMBus™, and SPI™ serial ports ...
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... C8051F310/1/2/3/4/5 2 Notes Rev. 1.5 ...
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... Analog to Digital Converter..................................................................... 31 1.8. Comparators ..................................................................................................... 32 2. Absolute Maximum Ratings .................................................................................. 33 3. Global DC Electrical Characteristics .................................................................... 34 4. Pinout and Package Definitions............................................................................ 35 5. 10-Bit ADC (ADC0, C8051F310/1/2/3 only) ........................................................... 43 5.1. Analog Multiplexer ............................................................................................ 44 5.2. Temperature Sensor ......................................................................................... 45 5.3. Modes of Operation .......................................................................................... 47 5.3.1. Starting a Conversion............................................................................... 47 5.3.2. Tracking Modes........................................................................................ 48 5 ...
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... C8051F310/1/2/3/4/5 8.3.4. Interrupt Latency ...................................................................................... 87 8.3.5. Interrupt Register Descriptions................................................................. 89 8.4. Power Management Modes .............................................................................. 94 8.4.1. Idle Mode.................................................................................................. 94 8.4.2. Stop Mode ................................................................................................ 95 9. Reset Sources......................................................................................................... 97 9.1. Power-On Reset ............................................................................................... 98 9.2. Power-Fail Reset / VDD Monitor....................................................................... 99 9.3. External Reset ................................................................................................ 100 9.4. Missing Clock Detector Reset......................................................................... 100 9.5. Comparator0 Reset......................................................................................... 100 9 ...
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... Counter/Timer ........................................................................................ 194 18.2.Capture/Compare Modules ............................................................................ 195 18.2.1.Edge-triggered Capture Mode................................................................ 196 18.2.2.Software Timer (Compare) Mode........................................................... 197 18.2.3.High-Speed Output Mode ...................................................................... 198 18.2.4.Frequency Output Mode ........................................................................ 199 18.2.5.8-Bit Pulse Width Modulator Mode......................................................... 200 18.2.6.16-Bit Pulse Width Modulator Mode....................................................... 201 18.3.Watchdog Timer Mode ................................................................................... 202 C8051F310/1/2/3/4/5 Rev. 1.5 5 ...
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... C8051F310/1/2/3/4/5 18.3.1.Watchdog Timer Operation .................................................................... 202 18.3.2.Watchdog Timer Usage ......................................................................... 203 18.4.Register Descriptions for PCA........................................................................ 205 19. Revision Specific Behavior ................................................................................. 211 19.1.Revision Identification..................................................................................... 211 19.2.Reset Behavior ............................................................................................... 211 19.2.1.Weak Pullups on GPIO Pins .................................................................. 211 19.2.2.VDD Monitor and the RST Pin ............................................................... 211 19.3.PCA Counter .................................................................................................. 212 20. C2 Interface ........................................................................................................... 213 20 ...
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... List of Figures 1. System Overview Figure 1.1. C8051F310 Block Diagram .................................................................... 19 Figure 1.2. C8051F311 Block Diagram .................................................................... 20 Figure 1.3. C8051F312 Block Diagram .................................................................... 21 Figure 1.4. C8051F313 Block Diagram .................................................................... 22 Figure 1.5. C8051F314 Block Diagram .................................................................... 23 Figure 1.6. C8051F315 Block Diagram .................................................................... 24 Figure 1.7. Comparison of Peak MCU Execution Speeds ....................................... 25 Figure 1 ...
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... C8051F310/1/2/3/4/5 9. Reset Sources Figure 9.1. Reset Sources........................................................................................ 97 Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 98 10. Flash Memory Figure 10.1. Flash Program Memory Map.............................................................. 105 11. External RAM 12. Oscillators Figure 12.1. Oscillator Diagram.............................................................................. 111 Figure 12.2. 32.768 kHz External Crystal Example................................................ 116 13 ...
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... Figure 18.8. PCA 8-Bit PWM Mode Diagram ......................................................... 200 Figure 18.9. PCA 16-Bit PWM Mode...................................................................... 201 Figure 18.10. PCA Module 4 with Watchdog Timer Enabled ................................. 202 19. Revision Specific Behavior Figure 19.1. Reading Package Marking ................................................................. 211 20. C2 Interface Figure 20.1. Typical C2 Pin Sharing....................................................................... 215 C8051F310/1/2/3/4/5 Rev. 1.5 9 ...
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... C8051F310/1/2/3/4/5 10 Notes Rev. 1.5 ...
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... Table 4.1. Pin Definitions for the C8051F31x .......................................................... 35 Table 4.2. LQFP-32 Package Dimensions .............................................................. 38 Table 4.3. MLP-28 Package Dimensions ................................................................ 40 5. 10-Bit ADC (ADC0, C8051F310/1/2/3 only) Table 5.1. ADC0 Electrical Characteristics .............................................................. 58 6. Voltage Reference (C8051F310/1/2/3 only) Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 60 7 ...
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... C8051F310/1/2/3/4/5 Table 15.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................................................ 161 Table 15.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator ...................................................................... 162 Table 15.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator ........................................................................ 162 16 ...
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... SFR Definition 12.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 115 SFR Definition 13.1. XBR0: Port I/O Crossbar Register 124 SFR Definition 13.2. XBR1: Port I/O Crossbar Register 125 SFR Definition 13.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 13.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 C8051F310/1/2/3/4/5 Rev. 1.5 13 ...
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... C8051F310/1/2/3/4/5 SFR Definition 13.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 127 SFR Definition 13.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SFR Definition 13.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SFR Definition 13.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SFR Definition 13.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 129 SFR Definition 13.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SFR Definition 13 ...
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... SFR Definition 18.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 209 C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 C2 Register Definition 20.2. DEVICEID: C2 Device 213 C2 Register Definition 20.3. REVID: C2 Revision 214 C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 214 C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 214 C8051F310/1/2/3/4/5 Rev. 1.5 15 ...
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... C8051F310/1/2/3/4/5 16 Notes Rev. 1.5 ...
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... True 10-bit 200 ksps 25-channel single-ended/differential ADC with analog multiplexer (C8051F310/1/2/3) • Precision programmable 25 MHz internal oscillator • (C8051F310/ (C8051F312/3/4/5) of on-chip Flash memory • 1280 bytes of on-chip RAM • SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware • ...
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... C8051F310/1/2/3/4/5 Table 1.1. Product Selection Guide C8051F310 25 16 1280 C8051F311 25 16 1280 C8051F312 25 8 1280 C8051F313 25 8 1280 C8051F314 25 8 1280 C8051F315 25 8 1280 Rev. 1.5 2 LQFP-32 2 MLP-28 2 LQFP-32 2 MLP-28 2 LQFP-32 2 MLP-28 ...
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... Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.1. C8051F310 Block Diagram C8051F310/1/2/3/4/5 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT ...
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... C8051F310/1/2/3/4/5 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.2. C8051F311 Block Diagram 20 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 0,1,2,3 / RTC 5 256 byte Reset SRAM PCA/ 1 WDT ...
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... Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.3. C8051F312 Block Diagram C8051F310/1/2/3/4/5 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT 1K byte SRAM ...
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... C8051F310/1/2/3/4/5 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.4. C8051F313 Block Diagram 22 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 Reset 256 byte SRAM PCA/ 1 WDT 1K byte ...
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... Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.5. C8051F314 Block Diagram C8051F310/1/2/3/4/5 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 256 byte SRAM PCA/ 1 WDT 1K byte SRAM ...
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... C8051F310/1/2/3/4/5 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.6. C8051F315 Block Diagram 24 Port 0 Latch Port 1 Latch UART Timer FLASH 0 0,1,2,3 / RTC 5 Reset 256 byte SRAM PCA/ 1 WDT 1K byte ...
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... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.7 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys- tem clocks Silicon Labs (25 MHz clk) Figure 1.7. Comparison of Peak MCU Execution Speeds C8051F310/1/2/3/4/5 2 2 Microchip Philips ...
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... C8051F310/1/2/3/4/5 1.1.3. Additional Features The C8051F31x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... Byte Sectors) 0x0000 C8051F312/3/4/5 RESERVED 0x2000 0x1FFF 8 kB Flash (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 1.9. On-Board Memory Map C8051F310/1/2/3/4/5 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) 0x80 0x7F (Direct and Indirect Addressing) 0x30 ...
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... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F310DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F31x MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, a serial adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply ...
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... Programmable Digital I/O and Crossbar C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port); C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port). The C8051F31x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config- ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “ ...
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... C8051F310/1/2/3/4/5 1.5. Serial Ports The C8051F31x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. ...
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... Analog to Digital Converter The C8051F310/1/2/3 devices include an on-chip 10-bit SAR ADC with a 25-channel differential input mul- tiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit accuracy with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and nega- tive ADC inputs. Ports1-3 are available as an ADC inputs ...
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... C8051F310/1/2/3/4/5 1.8. Comparators C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. ...
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... This is a stress rating only and functional operation of the devices at those or any other condi- tions above those indicated in the operation listings of this specification is not implied. Exposure to maxi- mum rating conditions for extended periods may affect device reliability. C8051F310/1/2/3/4/5 Conditions Min – ...
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... C8051F310/1/2/3/4/5 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40°C to +85°C, 25 MHz System Clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply Current with V DD CPU active V V Digital Supply Current with V DD CPU inactive (not accessing V Flash) ...
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... C8051F310/1/2/3/4/5 Type Description Power Supply Voltage. Ground. D I/O Device Reset. Open-drain output of internal POR. An exter- nal source can initiate a system reset by driving this pin low for at least 10 µs. D I/O Clock signal for the C2 Debug Interface. D I/O Port 3.0. See ...
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... C8051F310/1/2/3/4/5 Table 4.1. Pin Definitions for the C8051F31x (Continued) Pin Numbers Name ‘F310/2/4 ‘F311/3 P3.1 7 P3.2 8 P3 Type Description D I/O or Port 1.3. See Section I/O or Port 1.4. See Section I/O or Port 1.5. See Section 13 ...
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... P0 GND 4 VDD /RST/C2CK 5 6 P3.0/C2D 7 P3.1 8 P3.2 Figure 4.1. LQFP-32 Pinout Diagram (Top View) C8051F310/1/2/3/4/5 C8051F310/2/4 Top View Rev. 1.5 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 37 ...
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... C8051F310/1/2/3/4 PIN 1 IDENTIFIER Figure 4.2. LQFP-32 Package Diagram 38 Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. Rev. 1.5 MM TYP MAX - 1.60 - 0.15 1.40 1.45 0.37 0.45 9.00 - 7.00 - 0.80 - 9.00 - 7.00 - 0.60 0.75 ...
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... GND P0.1 1 P0.0 2 GND 3 C8051F311/3/5 VDD 4 /RST/C2CK 5 P3.0/C2D 6 P2.7 7 Figure 4.3. MLP-28 Pinout Diagram (Top View) C8051F310/1/2/3/4/5 Top View GND Rev. 1.5 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 39 ...
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... C8051F310/1/2/3/4/5 Bottom View DETAIL Side View DETAIL 1 Figure 4.4. MLP-28 Package Drawing Rev. 1.5 Table 4.3. MLP-28 Package Dimensions MM MIN TYP MAX A 0.80 0.90 1. 0.02 0. 0. 0.18 0. 2.90 3. 2.90 3. 0.45 0. 0.435 - BB - 0.435 ...
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... Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.5. Typical MLP-28 Landing Diagram C8051F310/1/2/3/4/5 Top View E2 E Rev. 1.5 0. ...
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... C8051F310/1/2/3/4/5 0.50 mm 0.60 mm 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.6. MLP-28 Solder Paste Recommendation 42 Top View 0.60 mm 0.30 mm 0. Rev. 1.5 0.85 mm ...
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... ADC (ADC0, C8051F310/1/2/3 only) The ADC0 subsystem for the C8051F310/1/2/3 consists of two analog multiplexers (referred to collectively as AMUX0) with 25 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...
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... C8051F310/1/2/3/4/5 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.4, the on-chip temperature sensor, or the positive power supply (V following may be selected as the negative input: P1.0-P3.4, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode ...
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... Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. C8051F310/1/2/3/4 3.35*(TEMP ) + 897 mV ...
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... C8051F310/1/2/3/4/5 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration 46 40.00 0.00 20.00 Temperature (degrees C) Rev. 1.5 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2.00 -3.00 -4.00 ...
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... CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Input/Output” on page 119 for details on Port I/O configuration. C8051F310/1/2/3/4/5 for timer configuration. Rev. 1.5 Section “13. Port ...
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... C8051F310/1/2/3/4/5 5.3.2. Tracking Modes According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode ...
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... TOTAL n is the ADC resolution in bits (10). Differential Mode MUX Select Px MUX Input MUX SAMPLE Px MUX MUX Select Figure 5.5. ADC0 Equivalent Input Circuits C8051F310/1/2/3/4/5 reduces See Table 5.1 for ADC0 minimum TOTAL MUX n 2 × ------ - = TOTAL SAMPLE SA ...
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... C8051F310/2; selection RESERVED on C8051F311/3 devices. 50 R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P1.0 P1.1 P1 ...
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... GND (ADC in Single-Ended Mode) †Only applies to C8051F310/2; selection RESERVED on C8051F311/3 devices. C8051F310/1/2/3/4/5 R/W R/W R/W AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit4 Bit3 Bit2 ADC0 Negative Input P1 ...
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... C8051F310/1/2/3/4/5 SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5 ...
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... Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved . C8051F310/1/2/3/4/5 R/W R/W R/W R/W ...
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... C8051F310/1/2/3/4/5 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
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... Bit5 Bits7-0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Less-Than Data Word. C8051F310/1/2/3/4/5 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W ...
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... C8051F310/1/2/3/4/5 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value ...
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... ADC0LTH:ADC0LTL 0x0FC0 0x0000 VREF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL 0xFF80 AD0WINT not affected 0x8000 -VREF Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data C8051F310/1/2/3/4/5 ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x01FF 0x0041 VREF x (64/512) 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) ...
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... C8051F310/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance (10 kHz sine-wave Single-ended input below Full Scale, 200 ksps) ...
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... Voltage Reference (C8051F310/1/2/3 only) The voltage reference MUX on C8051F310/1/2/3 devices is configurable to use an externally connected voltage reference, or the power supply voltage (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source, REFSL should be set to ‘0’; For V as the reference source, REFSL should be set to ‘ ...
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... C8051F310/1/2/3/4/5 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF input pin used as voltage reference. ...
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... CMX0N1 CP0HYP0 CMX0N0 CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 P1.0 P1.4 P2.0 P2.4 P1.1 P1.5 P2.1 P2.5 Figure 7.1. Comparator0 Functional Block Diagram C8051F310/1/2/3/4/5 123). Comparator0 may also be used as a 100). Section “13.3. General Purpose Port I/O” on page VDD CP0 + + SET SET ...
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... C8051F310/1/2/3/4/5 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis- abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA ...
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... Therefore recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. This Power Up Time is specified in Table 7.1 on page 70. C8051F310/1/2/3/4/5 + CP0 ...
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... C8051F310/1/2/3/4/5 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage on CP0+ > CP0-. Bit5: CP0RIF: Comparator0 Rising-Edge Interrupt Flag. ...
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... UNUSED. Read = 00b, Write = don’t care. Bits1-0: CMX0P1-CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 Positive Input C8051F310/1/2/3/4/5 R/W R/W R/W R CMX0P1 CMX0P0 00000000 Bit4 Bit3 Bit2 Bit1 P1.1 P1.5 P2 ...
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... C8051F310/1/2/3/4/5 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. Bit4: CP0FIE: Comparator Falling-Edge Interrupt Enable. ...
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... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1-0: CP1HYN1-0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F310/1/2/3/4/5 R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit4 Bit3 Bit2 Rev. 1.5 ...
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... C8051F310/1/2/3/4/5 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W R/W R CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits5-4: CMX1N1-CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. ...
Page 69
... Comparator falling-edge interrupt disabled. 1: Comparator falling-edge interrupt enabled. Bits1-0: CP1MD1-CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Mode CP1MD1 CP1MD0 C8051F310/1/2/3/4/5 R/W R/W R/W CP1FIE - - CP1MD1 CP1MD0 00000010 Bit4 Bit3 Bit2 CP1 Response Time (TYP) 0 Fastest Response Time 1 — ...
Page 70
... C8051F310/1/2/3/4/5 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Response Time: † Mode 0, Vcm = 1.5 V Response Time: † Mode 1, Vcm = 1.5 V Response Time: † Mode 2, Vcm = 1 ...
Page 71
... PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 8.1. CIP-51 Block Diagram C8051F310/1/2/3/4/5 Section 17), an enhanced full-duplex UART (see description Section 16), 256 bytes of internal RAM, 128 byte (Section 8.2.6), and 29 Port I/O (see description in - Extended Interrupt Handler ...
Page 72
... C8051F310/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
Page 73
... Subtract indirect RAM from A with borrow SUBB A, #data Subtract immediate from A with borrow INC A Increment A INC Rn Increment register INC direct Increment direct byte INC @Ri Increment indirect RAM DEC A Decrement A C8051F310/1/2/3/4/5 Section “10. Flash Memory” on page 103 Arithmetic Operations Rev. 1.5 for Clock Bytes Cycles ...
Page 74
... C8051F310/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct ...
Page 75
... Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR JZ rel Jump if A equals zero C8051F310/1/2/3/4/5 Boolean Manipulation Program Branching Rev. 1.5 Clock Bytes Cycles ...
Page 76
... C8051F310/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal Compare immediate to Register and jump if not ...
Page 77
... Byte Sectors) 0x0000 8.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F310/1 and C8051F312/3/4/5 imple- ment 16 and 8 kB, respectively, of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF or 0x0000 to 0x1FFF. ...
Page 78
... C8051F310/1/2/3/4/5 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
Page 79
... SCON0 SBUF0 CPT1CN 90 P1 TMR3CN TMR3RLL 88 TCON TMOD TL0 DPL 0(8) 1(9) 2(A) (bit addressable) C8051F310/1/2/3/4/5 PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN P2MDIN P3MDIN IT01CF P0SKIP P1SKIP TMR2RLH TMR2L TMR2H ADC0GTL ADC0GTH ADC0LTL AMX0P ADC0CF ADC0L OSCICL SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT ...
Page 80
... C8051F310/1/2/3/4/5 Table 8.3. Special Function Registers Register Address Description SFRs are listed in alphabetical order. All undefined SFR locations are reserved ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ...
Page 81
... Timer/Counter 1 High TL0 0x8A Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TMOD 0x89 Timer/Counter Mode TMR2CN 0xC8 Timer/Counter 2 Control TMR2H 0xCD Timer/Counter 2 High C8051F310/1/2/3/4/5 Rev. 1.5 Page 131 131 132 132 205 209 209 209 209 209 208 208 208 208 ...
Page 82
... C8051F310/1/2/3/4/5 Table 8.3. Special Function Registers (Continued) Register Address Description TMR2L 0xCC Timer/Counter 2 Low TMR2RLH 0xCB Timer/Counter 2 Reload High TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low TMR3RLH 0x93 Timer/Counter 3 Reload High ...
Page 83
... R/W R/W Bit7 Bit6 Bit5 Bits7-0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. C8051F310/1/2/3/4/5 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ...
Page 84
... C8051F310/1/2/3/4/5 SFR Definition 8.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 85
... SFR Definition 8. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. C8051F310/1/2/3/4/5 R/W R/W R/W R/W B.4 B.3 B.2 B.1 Bit4 Bit3 Bit2 Bit1 Rev. 1.5 R/W Reset Value B ...
Page 86
... C8051F310/1/2/3/4/5 8.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 14 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt- pending flag(s) located in an SFR ...
Page 87
... DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. C8051F310/1/2/3/4/5 (Section “17.1. Timer 0 and Timer 1” on page IT1 ...
Page 88
... C8051F310/1/2/3/4/5 Table 8.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED 0x0043 ADC0 Window Compare 0x004B ADC0 Conversion ...
Page 89
... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. C8051F310/1/2/3/4/5 R/W R/W R/W R/W ES0 ET1 ...
Page 90
... C8051F310/1/2/3/4/5 SFR Definition 8.8. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. ...
Page 91
... Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). Bit1: RESERVED. Read = 0. Must Write 0. Bit0: ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051F310/1/2/3/4/5 R/W R/W R/W EPCA0 EADC0 EWADC0 Reserved Bit4 ...
Page 92
... C8051F310/1/2/3/4/5 SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0F Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. ...
Page 93
... Port pin to a peripheral configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN0SL2-0 /INT0 Port Pin 000 001 010 011 100 101 110 111 C8051F310/1/2/3/4/5 R/W R/W R/W IN1SL0 IN0PL IN0SL2 IN0SL1 Bit4 Bit3 Bit2 P0.0 P0 ...
Page 94
... C8051F310/1/2/3/4/5 8.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states ...
Page 95
... IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051F310/1/2/3/4/5 R/W R/W R/W ...
Page 96
... C8051F310/1/2/3/4/5 96 Notes Rev. 1.5 ...
Page 97
... Px.x C0RSEF Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Extended Interrupt Handler C8051F310/1/2/3/4/5 for information on selecting and configuring details the use of the Watchdog Timer). VDD Power On Reset Supply Monitor + '0' - Enable PCA WDT (Software Reset) SWRSF EN System Reset Figure 9 ...
Page 98
... C8051F310/1/2/3/4/5 9.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as the V RST ramp time increases (V ramp time is defined as how fast V ...
Page 99
... Bit6: V STAT: V Status This bit indicates the current power supply status ( below the above the Bits5-0: Reserved. Read = Variable. Write = don’t care. C8051F310/1/2/3/4/5 Monitor to drop below V DD monitor is enabled and a software reset is performed, the DD monitor. DD Monitor Control Bit4 Bit3 Bit2 monitor circuit on/off ...
Page 100
... A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX write operation targets an address above address 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5. • A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address above address 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5. • ...
Page 101
... Read: Last reset was not a power- reset source. 1: Read: Last reset was a power- Write: V monitor is a reset source. DD Bit0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not RST pin. 1: Source of last reset was RST pin. C8051F310/1/2/3/4/5 R/W R R/W SWRSF WDTRSF MCDRSF PORSF Bit4 Bit3 Bit2 monitor reset ...
Page 102
... C8051F310/1/2/3/4/5 Table 9.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I RST Output Low Voltage OL RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 Monitor Threshold ( RST Time from last system clock rising Missing Clock Detector Timeout ...
Page 103
... Step 3. Set the PSWE bit (register PSCTL). Step 4. Write the first key code to FLKEY: 0xA5. Step 5. Write the second key code to FLKEY: 0xF1. Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. C8051F310/1/2/3/4/5 Section “20. C2 Interface” Rev. 1.5 Monitor DD ...
Page 104
... V; –40 to +85 °C unless otherwise specified. DD Parameter C8051F310/1 Flash Size C8051F312/3/4/5 Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock † Note: 512 bytes at locations 0x3E00 (C8051F310/1) are reserved. 104 Conditions Min † 16384 8192 Rev. 1.5 Section ...
Page 105
... The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. C8051F310/1/2/3/4/5 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) ...
Page 106
... C8051F310/1/2/3/4/5 Accessing Flash from the C2 debug interface: 1. Any unlocked page may be read, written, or erased. 2. Locked pages cannot be read, written, or erased. 3. The page containing the Lock Byte may be read, written, or erased unlocked. 4. Reading the contents of the Lock Byte is always permitted. 5. Locking additional pages (changing '1's to '0's in the Lock Byte) is not permitted. ...
Page 107
... Read: When read, bits 1-0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. C8051F310/1/2/3/4/5 R/W R/W R/W R ...
Page 108
... C8051F310/1/2/3/4/5 SFR Definition 10.3. FLSCL: Flash Scale R/W R/W R/W FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads ...
Page 109
... MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. C8051F310/1/2/3/4/5 Section “10. Flash Memory” on page 103 R/W R/W ...
Page 110
... C8051F310/1/2/3/4/5 110 Notes Rev. 1.5 ...
Page 111
... Electrical specifications for the precision internal oscillator are given in Table 12.1 on page 113. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. C8051F310/1/2/3/4/5 OSCICL OSCICN ...
Page 112
... C8051F310/1/2/3/4/5 SFR Definition 12.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6-0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. This reset value for OSCICL deter- mines the oscillator base frequency ...
Page 113
... SYSCLK derived from the External Oscillator circuit. Table 12.1. Internal Oscillator Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified. DD Parameter Internal Oscillator Frequency Internal Oscillator Supply Current (from C8051F310/1/2/3/4/5 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Conditions Min 24 OSCICN ...
Page 114
... C8051F310/1/2/3/4/5 12.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 12. MΩ ...
Page 115
... R = Pullup resistor value in kΩ C MODE (Circuit from Figure 12.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where frequency of clock in MHz C = capacitor value the XTAL2 pin Power Supply on MCU in volts DD C8051F310/1/2/3/4/5 R/W R R/W R/W XFCN2 XFCN1 Bit4 Bit3 Bit2 Bit1 RC (XOSCMD = 10x) f ≤ ...
Page 116
... C8051F310/1/2/3/4/5 12.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 12.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 12.4. For example ...
Page 117
... Assume pF MHz 150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 12 22 150 = 0.146 MHz, or 146 kHz Therefore, the XFCN value to use in this example is 011b. C8051F310/1/2/3/4/5 Rev. 1.5 = 3.0 V and DD 117 ...
Page 118
... C8051F310/1/2/3/4/5 118 Notes Rev. 1.5 ...
Page 119
... Port Input/Output Digital and analog resources are available through 29 I/O pins (C8051F310/2/ I/O pins (C8051F311/3/5). Port pins are organized as three byte-wide Ports and one 5-bit (C8051F310/2/4) or 1-bit (C8051F311/3/5) Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 13.3. ...
Page 120
... C8051F310/1/2/3/4/5 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT Figure 13.2. Port I/O Cell Block Diagram 120 VDD GND Analog Select Rev. 1.5 VDD (WEAK) PORT PAD ...
Page 121
... SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. † NSS is only pinned out in 4-wire SPI mode. Figure 13.3. Crossbar Priority Decoder with No Pins Skipped C8051F310/1/2/3/4 ...
Page 122
... C8051F310/1/2/3/4 Signals PIN I TX0 RX0 SCK MISO MOSI NSS† SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI P0SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. † ...
Page 123
... Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051F310/1/2/3/4/5 Rev. 1.5 123 ...
Page 124
... C8051F310/1/2/3/4/5 SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. ...
Page 125
... CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. C8051F310/1/2/3/4/5 R/W R/W R/W R/W T0E ...
Page 126
... C8051F310/1/2/3/4/5 13.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin ...
Page 127
... These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. C8051F310/1/2/3/4/5 R/W R/W R/W R/W ...
Page 128
... C8051F310/1/2/3/4/5 SFR Definition 13.7. P1: Port1 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘1’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input ...
Page 129
... These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. C8051F310/1/2/3/4/5 R/W R/W R/W R/W ...
Page 130
... C8051F310/1/2/3/4/5 SFR Definition 13.11. P2: Port2 R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit5 Bits7-0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘1’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input ...
Page 131
... Read - Always reads ‘1’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. 0: P3.n pin is logic low. 1: P3.n pin is logic high. Note: Only P3.0-P3.4 are associated with Port pins on C8051F10/2/4 devices; Only P3.0 is associated with a Port pin on C8051F311/3/5 devices. C8051F310/1/2/3/4/5 R/W R/W R/W R/W - ...
Page 132
... C8051F310/1/2/3/4/5 SFR Definition 13.16. P3MDIN: Port3 Input Mode R/W R/W R Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bits4-0: Input Configuration Bits for P3.4-P3.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled ...
Page 133
... Port I/O push-pull -10 µA, Port I/O push-pull Output High Voltage -10 mA, Port I/O push-pull OH Output Low Voltage Input High Voltage Input Low Voltage Weak Pullup Off Input Leakage Current Weak Pullup On, V C8051F310/1/2/3/4/5 Conditions Min V – 0 – 0.1 DD — 8.5 mA — µ ...
Page 134
... C8051F310/1/2/3/4/5 134 Notes Rev. 1.5 ...
Page 135
... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation Figure 14.1. SMBus Block Diagram C8051F310/1/2/3/4 Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL Control Data Path SDA Control Control SMB0DAT FILTER Rev. 1.5 SCL ...
Page 136
... C8051F310/1/2/3/4/5 14.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: • The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. • The I2C-Bus Specification—Version 2.0, Philips Semiconductor. • System Management Bus Specification—Version 1.1, SBS Implementers Forum. ...
Page 137
... LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win- ning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. C8051F310/1/2/3/4/5 SLA5-0 R/W D7 ...
Page 138
... C8051F310/1/2/3/4/5 14.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency ...
Page 139
... Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in tion Register” on page 140. C8051F310/1/2/3/4/5 for more details on transmission 143; Table 14.4 provides a quick SMB0CN decoding refer- Section “14.4.1. SMBus Configura- Rev. 1.5 Section 139 ...
Page 140
... C8051F310/1/2/3/4/5 14.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins ...
Page 141
... SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 14.4). When a Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). C8051F310/1/2/3/4/5 T SCL High Timeout High Minimum SDA Hold Time – ...
Page 142
... C8051F310/1/2/3/4/5 SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. ...
Page 143
... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 14.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 14.4 for SMBus sta- tus decoding using the SMB0CN register. C8051F310/1/2/3/4/5 Rev. 1.5 143 ...
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... C8051F310/1/2/3/4/5 SFR Definition 14.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. ...
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... ACK/NACK received. SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F310/1/2/3/4/5 Cleared by Hardware When... • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • ...
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... C8051F310/1/2/3/4/5 14.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
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... Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 14.5. Typical Master Transmitter Sequence C8051F310/1/2/3/4 Data Byte A Data Byte Interrupt Interrupt S = START P = STOP ...
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... C8051F310/1/2/3/4/5 14.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...
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... Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 14.7. Typical Slave Receiver Sequence C8051F310/1/2/3/4/5 A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev ...
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... C8051F310/1/2/3/4/5 14.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set ...
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... ACK received. A master data byte was 1000 received; ACK requested. C8051F310/1/2/3/4/5 Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...
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... C8051F310/1/2/3/4/5 Table 14.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted error detected. A STOP was detected while 0101 addressed Slave Transmit- ter. A slave address was ...
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... CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). Write to SBUF UART Baud Rate Generator Figure 15.1. UART0 Block Diagram C8051F310/1/2/3/4/5 154). Received data buffering allows SFR Bus TB8 SBUF SET (TX Shift) D ...
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... C8051F310/1/2/3/4/5 15.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 15.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
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... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 BIT SPACE BIT TIMES BIT SAMPLING Figure 15.4. 8-Bit UART Timing Diagram C8051F310/1/2/3/4/5 TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR OR TX ...
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... C8051F310/1/2/3/4/5 15.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
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... Master Device Device Figure 15.6. UART Multi-Processor Mode Interconnect Diagram C8051F310/1/2/3/4/5 Slave Slave Device Rev. 1.5 Slave Device ...
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... C8051F310/1/2/3/4/5 SFR Definition 15.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b. Write = don’ ...
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... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con- tents of the receive latch. C8051F310/1/2/3/4/5 R/W R/W R/W ...
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... C8051F310/1/2/3/4/5 Table 15.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% † SCA1-SCA0 and T1M bit definitions can be found in Table 15 ...
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... SCA1-SCA0 and T1M bit definitions can be found in C8051F310/1/2/3/4/5 Oscillator Frequency: 22.1184 MHz Oscilla- Timer Clock SCA1-SCA0 tor Divide Source (pre-scale Factor select) 96 SYSCLK XX 192 SYSCLK XX ...
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... C8051F310/1/2/3/4/5 Table 15.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 ...
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... I/O pins can be used to select multiple slave devices in master mode. SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer 7 6 Receive Data Buffer Write SPI0DAT SFR Bus Figure 16.1. SPI Block Diagram C8051F310/1/2/3/4/5 SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK ...
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... C8051F310/1/2/3/4/5 16.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 16.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
Page 165
... SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 16.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. C8051F310/1/2/3/4/5 Rev. 1.5 165 ...
Page 166
... C8051F310/1/2/3/4/5 Master Device 1 Figure 16.2. Multiple-Master Mode Connection Diagram Master Device Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram 166 NSS GPIO MISO MISO Master MOSI ...
Page 167
... The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. C8051F310/1/2/3/4/5 Rev. 1.5 167 ...
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... C8051F310/1/2/3/4/5 16.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock ...
Page 169
... NSS (4-Wire Mode) Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) C8051F310/1/2/3/4/5 Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 6 ...
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... C8051F310/1/2/3/4/5 16.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following register definitions ...
Page 171
... SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. C8051F310/1/2/3/4/5 R/W R/W R/W TXBMT Bit4 Bit3 ...
Page 172
... C8051F310/1/2/3/4/5 SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register ...
Page 173
... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.9. SPI Master Timing (CKPHA = 1) C8051F310/1/2/3/4/5 T MCKL T T MIS MIH T MCKL T MIH Rev ...
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... C8051F310/1/2/3/4/5 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...
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... MOSI Valid to SCK Sample Edge SIS T SCK Sample Edge to MOSI Change SIH T SCK Shift Edge to MISO Change SOH Last SCK Edge to MISO Change T SLH (CKPHA = 1 ONLY) † equal to one period of the device system clock (SYSCLK). SYSCLK C8051F310/1/2/3/4/5 Min SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK — ...
Page 176
... C8051F310/1/2/3/4/5 176 Notes Rev. 1.5 ...
Page 177
... As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. C8051F310/1/2/3/4/5 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Rev ...
Page 178
... C8051F310/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “13.1. Priority Crossbar Decoder” on page 121 pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock ...
Page 179
... TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register IT01CF (see for details on the external input signals /INT0 and /INT1). Pre-scaled Clock SYSCLK T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 17.2. T0 Mode 2 Block Diagram C8051F310/1/2/3/4/5 Section “8.3.2. External Interrupts” on page 87 CKCON TMOD INT01CF ...
Page 180
... C8051F310/1/2/3/4/5 17.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 181
... IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 8.11). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. C8051F310/1/2/3/4/5 R/W R/W R/W R/W TR0 ...
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... C8051F310/1/2/3/4/5 SFR Definition 17.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis- ter IT01CF (see SFR Definition 8 ...
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... SCA1 SCA0 Note: External clock divided synchronized with the system clock, and the external clock must be less than or equal to the system clock to operate in this mode. C8051F310/1/2/3/4/5 R/W R/W R/W T2ML T1M T0M SCA1 Bit4 Bit3 Bit2 Prescaled Clock System clock divided by 12 ...
Page 184
... C8051F310/1/2/3/4/5 SFR Definition 17.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 17.5. TL1: Timer 1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL1: Timer 1 Low Byte ...
Page 185
... CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 17.4. Timer 2 16-Bit Mode Block Diagram C8051F310/1/2/3/4/5 To SMBus TMR2L Overflow TCLK TR2 TMR2L TMR2H TMR2RLL TMR2RLH Reload Rev. 1.5 To ADC, SMBus TF2H Interrupt TF2L TF2LEN T2SPLIT TR2 T2XCLK 185 ...
Page 186
... C8051F310/1/2/3/4/5 17.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control TMR2H. TMR2L is always running when configured for 8-bit Mode ...
Page 187
... Timer 2 external clock selection is the system clock divided by 12. 1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. C8051F310/1/2/3/4/5 R/W R/W R/W ...
Page 188
... C8051F310/1/2/3/4/5 SFR Definition 17.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition 17.10. TMR2RLH: Timer 2 Reload Register High Byte ...
Page 189
... CKCON T3XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 17.6. Timer 3 16-Bit Mode Block Diagram C8051F310/1/2/3/4/5 TCLK TR3 TMR3L TMR3H TMR3RLL TMR3RLH Reload Rev. 1.5 To ADC TF3H Interrupt TF3L TF3LEN T3SPLIT TR3 T3XCLK 189 ...
Page 190
... C8051F310/1/2/3/4/5 17.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control TMR3H. TMR3L is always running when configured for 8-bit Mode ...
Page 191
... Timer 3 external clock selection is the system clock divided by 12. 1: Timer 3 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. C8051F310/1/2/3/4/5 R/W R/W R/W ...
Page 192
... C8051F310/1/2/3/4/5 SFR Definition 17.14. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. SFR Definition 17.15. TMR3RLH: Timer 3 Reload Register High Byte ...
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... Section 18.3 for details. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 Capture/Compare Capture/Compare Module 0 Figure 18.1. PCA Block Diagram C8051F310/1/2/3/4/5 for details on configuring the Crossbar). The counter/timer is driven by PCA 16-Bit Counter/Timer CLOCK MUX Capture/Compare Capture/Compare Module 1 Module 2 Crossbar Port I/O Rev. 1.5 Section “ ...
Page 194
... C8051F310/1/2/3/4/5 18.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. ...
Page 195
... ECCF0 PCA Module 0 (CCF0) ECCF1 PCA Module 1 (CCF1) ECCF2 PCA Module 2 (CCF2) ECCF3 PCA Module 3 (CCF3) ECCF4 PCA Module 4 (CCF4) Figure 18.3. PCA Interrupt Block Diagram C8051F310/1/2/3/4/5 MAT TOG PWM ECCF Capture triggered by positive edge CEXn Capture triggered by negative edge CEXn ...
Page 196
... C8051F310/1/2/3/4/5 18.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge) ...
Page 197
... Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Write to PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn Figure 18.5. PCA Software Timer Mode Diagram C8051F310/1/2/3/4 PCA0CPLn PCA0CPHn Enable 16-bit Comparator PCA PCA0L PCA0H Timebase Rev. 1.5 PCA Interrupt PCA0CN Match 1 197 ...
Page 198
... C8051F310/1/2/3/4/5 18.2.3. High-Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High- Speed Output mode ...
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... M T Write PCA0CPHn ENB Figure 18.7. PCA Frequency Output Mode C8051F310/1/2/3/4/5 F PCA ---------------------------------------- - F = CEXn × 2 PCA0CPHn E C PCA0CPLn 8-bit Adder C F Adder n Enable Toggle x 8-bit match Enable Comparator PCA Timebase PCA0L Rev. 1.5 is the fre- PCA PCA0CPHn TOGn 0 CEXn Crossbar Port I/O ...
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... C8051F310/1/2/3/4/5 18.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. ...