C8051F310-GQR Silicon Laboratories Inc, C8051F310-GQR Datasheet - Page 92
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C8051F310-GQR
Manufacturer Part Number
C8051F310-GQR
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Specifications of C8051F310-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
336-1445 - ADAPTER PROGRAM TOOLSTICK F310336-1329 - KIT REF DESIGN SENSORLESS BLDC336-1253 - DEV KIT FOR C8051F310/F311
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F310-GQR
Manufacturer:
SILICON
Quantity:
3 300
Company:
Part Number:
C8051F310-GQR
Manufacturer:
SILICON41
Quantity:
120
Company:
Part Number:
C8051F310-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F310-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F310/1/2/3/4/5/6/7
92
Bit7:
Bit6:
Bit5:
Bits4–3: RS1–RS0: Register Bank Select.
Bit2:
Bit1:
Bit0:
Bits7–0: ACC: Accumulator.
ACC.7
R/W
R/W
CY
Bit7
Bit7
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic opera-
tions.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
OV: Overflow Flag.
This bit is set to 1 under the following circumstances: an ADD, ADDC, or SUBB instruction
causes a sign-change overflow, a MUL instruction results in an overflow (result is greater
than 255), or a DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0
by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
This register is the accumulator for arithmetic operations.
RS1
ACC.6
0
0
1
1
R/W
R/W
AC
Bit6
Bit6
SFR Definition 8.4. PSW: Program Status Word
RS0
0
1
0
1
ACC.5
R/W
SFR Definition 8.5. ACC: Accumulator
R/W
Bit5
Bit5
F0
Register Bank
ACC.4
RS1
R/W
R/W
Bit4
Bit4
0
1
2
3
Rev. 1.7
ACC.3
RS0
R/W
R/W
Bit3
Bit3
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F
Address
ACC.2
R/W
R/W
OV
Bit2
Bit2
ACC.1
R/W
R/W
Bit1
Bit1
F1
(bit addressable)
(bit addressable)
PARITY
ACC.0
R/W
Bit0
Bit0
R
SFR Address:
SFR Address:
00000000
Reset Value
00000000
Reset Value
0xD0
0xE0