C8051F310-GQR Silicon Laboratories Inc, C8051F310-GQR Datasheet - Page 85
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C8051F310-GQR
Manufacturer Part Number
C8051F310-GQR
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Specifications of C8051F310-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
336-1445 - ADAPTER PROGRAM TOOLSTICK F310336-1329 - KIT REF DESIGN SENSORLESS BLDC336-1253 - DEV KIT FOR C8051F310/F311
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F310-GQR
Manufacturer:
SILICON
Quantity:
3 300
Company:
Part Number:
C8051F310-GQR
Manufacturer:
SILICON41
Quantity:
120
Company:
Part Number:
C8051F310-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F310-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
8.2.
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 8.2.
8.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F310/1 and C8051F312/3/4/5 imple-
ment 16 and 8 kB, respectively, of this program memory space as in-system, re-programmable Flash
memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF or 0x0000 to 0x1FFF.
Addresses above 0x3E00 are reserved on the 16 kB devices.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to
Memory Organization
0x3DFF
0x1FFF
0x3E00
0x0000
0x2000
0x0000
PROGRAM/DATA MEMORY
Programmable in 512
Programmable in 512
C8051F312/3/4/5
C8051F310/1
Byte Sectors)
Byte Sectors)
RESERVED
RESERVED
16 kB Flash
(In-System
(In-System
8 kB Flash
(Flash)
Section “10. Flash Memory” on page 111
Figure 8.2. Memory Map
0xFFFF
0x03FF
0x0400
0x0000
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
Rev. 1.7
XRAM - 1024 Bytes
0x0000 to 0x03FF, wrapped
(accessable using MOVX
Same 1024 bytes as from
(Indirect Addressing
C8051F310/1/2/3/4/5/6/7
(Direct and Indirect
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
General Purpose
Upper 128 RAM
on 1 kB boundaries
Bit Addressable
Addressing)
instruction)
Registers
Only)
DATA MEMORY (RAM)
for further details.
(Direct Addressing Only)
Special Function
Lower 128 RAM
(Direct and Indirect
Addressing)
Register's
85