C8051F310-GQR Silicon Laboratories Inc, C8051F310-GQR Datasheet - Page 158
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C8051F310-GQR
Manufacturer Part Number
C8051F310-GQR
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Specifications of C8051F310-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
336-1445 - ADAPTER PROGRAM TOOLSTICK F310336-1329 - KIT REF DESIGN SENSORLESS BLDC336-1253 - DEV KIT FOR C8051F310/F311
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F310-GQR
Manufacturer:
SILICON
Quantity:
3 300
Company:
Part Number:
C8051F310-GQR
Manufacturer:
SILICON41
Quantity:
120
Company:
Part Number:
C8051F310-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F310-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F310/1/2/3/4/5/6/7
14.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direc-
tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the
slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial
data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write
the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit gen-
erates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last
byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and
a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written
while an active Master Receiver. Figure 14.6 shows a typical Master Receiver sequence. Two received
data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’
interrupts occur before the ACK cycle in this mode.
158
Interrupt
S
Figure 14.6. Typical Master Receiver Sequence
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
R
Interrupt
A
Data Byte
Rev. 1.7
Interrupt
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
N
P