C8051F301-GS Silicon Laboratories Inc, C8051F301-GS Datasheet - Page 51

• Manufacturer Part Number: C8051F301-GS
• Description: IC 8051 MCU 8K FLASH 14-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F301-GS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F300DK
• Minimum Operating Temperature: - 40 C
• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051F30x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300336-1319 - REFERENCE DESIGN STEPPER MOTOR
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1536-5

7.
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in
Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer,
and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an
asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system
clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull
(see
source (see
The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-
CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see
Section “12.2. Port I/O Initialization” on page
Comparator0
CMX0N1
CMX0N0
CMX0P1
CMX0P0
Section “9.5. Comparator0 Reset” on page
Figure 7.1. Comparator0 Functional Block Diagram
P0.0
P0.2
P0.4
P0.6
P0.1
P0.3
P0.5
P0.7
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0EN
CP0FIF
CP0 +
CP0 -
CP0MD1
CP0MD0
Section “12.3. General Purpose Port I/O” on page
Rev. 2.9
+
-
GND
VDD
106). Comparator0 may also be used as a reset
85).
Decision
Reset
Tree
C8051F300/1/2/3/4/5
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Interrupt Flag
Rising-edge
CP0
Crossbar
Interrupt
Logic
Interrupt Flag
Falling-edge
CP0
CP0A
CP0
108).
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