C8051F305-GM Silicon Laboratories Inc, C8051F305-GM Datasheet - Page 111

• Manufacturer Part Number: C8051F305-GM
• Description: IC 8051 MCU 2K FLASH 11QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F305-GM

• Program Memory Type: FLASH
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 11-VQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F300DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• No. Of I/o's: 8
• Ram Memory Size: 256Byte
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 11QFN EP
• Device Core: 8051
• Family Name: C8051F30x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1251

13. SMBus
The SMBus I/O interface is a two-wire bidirectional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock operating as
master or slave (this can be faster than allowed by the SMBus specification, depending on the system
clock used). A method of extending the clock-low duration is available to accommodate devices with differ-
ent speed capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus:
SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data
register, used for both transmitting and receiving SMBus data and slave addresses.
M
R
A
S
T
E
Interrupt
Request
M
O
D
T
X
E
SMB0CN
S
A
T
S
O
T
A
C
K
R
Q
A
R
B
O
S
T
L
A
C
K
S
I
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
IRQ Generation
SMBUS CONTROL LOGIC
E
N
S
M
B
Figure 13.1. SMBus Block Diagram
N
H
I
SMB0CF
B
U
S
Y
E
X
T
H
O
D
L
M
O
S
B
T
E
7
M
S
B
F
T
E
6
SMB0DAT
B
A
U
D
1
5
U
D
B
A
0
4
Data Path
3
Control
2
1
Rev. 2.9
0
00
01
10
11
Control
Control
SDA
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
C8051F300/1/2/3/4/5
FILTER
FILTER
2
N
C serial bus. Reads and writes to
N
SDA
SCL
C
R
O
S
S
B
A
R
Port I/O
111