Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 335

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

Table 171. Status Register (DBGSTAT)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
Status Register
R/W1C
RDRF
The
RDRF—Receive data register full
This bit reflects the status of the Receive Data register. When data is written to the Receive
Data register, or data is transferred from the shift register to the Receive Data register, this
bit is set to one. When the Receive Data register is read, this bit is cleared to zero. This bit
is also cleared to zero by writing a one to this bit.
0 = Receive Data register is empty.
1 = Receive Data register is full.
RXOV—Receive overrun
This bit is set when a Receive Overrun occurs. A Receive Overrun occurs when there is
data in the Receive Data register and another byte is written to this register.
0 = Receive Overrun has not occurred
1 = Receive Overrun has occurred.
RXFE—Receive Framing error
This bit is set when a Receive Framing error has been detected. This bit is cleared by 
writing a one to this bit.
0 = No Framing Error detected.
1 = Receive Framing Error detected.
RXBRK—Receive Break detect
This bit is set when a Break condition has been detected. This occurs when 10 or more bits
received are Low. This bit is cleared by writing a one to this bit.
0 = No Break detected.
1 = Break detected.
TDRE—Transmit Data Register empty
This bit reflects the status of the Transmit Data register. When the Transmit Data register
is written, this bit is cleared to zero. When data from the transmit data register is read or
transferred to the transmit shift register, this bit is set to one. This bit is written to one to
abort the transmission of data being held in the transmit data register.
0 = Transmit Data register is full.
1 = Transmit Data register is empty.
7
0
Status Register (DBGSTAT)
R/W1C
RXOV
6
0
R/W1C
RXFE
5
0
P R E L I M I N A R Y
RXBRK
R/W1C
contains status information about the state of the UART.
4
0
FF_E085
R/W1S
TDRE
3
1
TXCOL
R/W1C
2
0
Product Specification
ZNEO
RXBUSY
On-Chip Debugger
R
1
0
Z16F Series
TXBUSY
R
0
0
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