Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 313

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

Table 162. IPO Trim 1 (IPOTRIM1)
Table 163. IPO Trim 2 (IPOTRIM2)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
BITS
FIELD
RESET
R/W
ADDR
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
Information Area
IPO Trim registers (Information Area Address 0021H and 0022H)
R/W
R/W
7
L
7
L
Reserved
These option bits are reserved for future use and must always be 1. This setting is the
default for unprogrammed (erased) Flash.
Data in the information area of memory cannot be altered directly. If you wish to alter the
factory settings, it must be done by writing to the Register Address identified. The part
defaults to the factory settings after reset and the registers must be re-written to have the
user settings in effect. Read the information area address to determine the factory 
settings.
Table 162
accessing the IPOTRIM1 and IPOTRIM2 registers.
The IPO Trim table is TBD.
R/W
R/W
and
6
L
6
L
Table 163
IPO TEMP TRIM
R/W
R/W
5
5
L
L
define the IPO Trim settings. They are altered after reset by
P R E L I M I N A R Y
R/W
R/W
FFFF_FF25H
4
L
4
L
FFFF_FF26
IPO TRIM
R/W
R/W
3
3
L
L
R/W
R/W
2
L
2
L
Product Specification
ZNEO
R/W
R/W
1
1
L
L
IPO TRIM
Z16F Series
Option Bits
R/W
R/W
0
L
0
L
297