Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 165

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

PS022008-0810
LIN-UART DMA Interface
LIN-UART Baud Rate Generator
action allows the BRG to function as an additional counter if the LIN-UART receiver
functionality is not employed. The transmitter is enabled in this mode.
The DMA engine is configured to move UART transmit and/or receive data. This reduces
processor overhead, especially when moving blocks of data. The DMA interface on the
LIN-UART consists of the
RxDmaAck
requests.
If transmit data is to be moved by the DMA, the transmit interrupt must be disabled in the
interrupt controller. If receive data is to be moved by the DMA, the RDAIRQ bit in the
LIN-UART Control 1 register must be set. This disables receive data interrupts when still
enabling error interrupts. The receive interrupt must be enabled in the interrupt controller to
process error condition interrupts.
The LIN-UART baud rate generator creates a lower frequency baud rate clock for data
transmission. The input to the BRG is the system clock. The LIN-UART baud rate high and
low byte registers combine to create a 16-bit baud rate divisor value (
sets the data transmission rate (baud rate) of the LIN-UART. The LIN-UART data rate is
calculated using the following equation for normal UART operation:
The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:
When the LIN-UART is disabled, the BRG functions as a basic 16-bit timer with interrupt
on timeout. Follow the steps below to configure BRG as a timer with interrupt on timeout:
1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART control 0
2. Load the appropriate 16-bit count value into the LIN-UART baud rate high and low
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
UART Data Rate (bps)
UART Data Rate (bps)
register to 0 (TEN bit is asserted, transmit activity may occur).
byte registers.
the LIN-UART Control1 register to 1. Enable the UART receive interrupt in the
interrupt controller.
inputs. Any of the DMA channels are configured to process the UART DMA
P R E L I M I N A R Y
TxDmaReq
=
=
--------------------------------------------------------------------------------- -
UART Baud Rate Divisor Value
--------------------------------------------------------------------------------------------- -
16 UART Baud Rate Divisor Value
System Clock Frequency (Hz)

System Clock Frequency (Hz)
and
RxDmaReq
outputs, and the
Product Specification
ZNEO
BRG[15:0]
TxDmaAck
Z16F Series
LIN-UART
) which
and
149