LH7A404N0F000B3;55 NXP Semiconductors, LH7A404N0F000B3;55 Datasheet - Page 7

• Manufacturer Part Number: LH7A404N0F000B3;55
• Description: IC ARM9 BLUESTREAK MCU 324LFBGA
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B3;55

• Package / Case: 324-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, Microwire, MMC, PS2, SmartCard, SPI, SSI, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH7A4
• Core: ARM9TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4335; 935285069557; LH7A404N0F000B3

32-Bit System-on-Chip
Preliminary data sheet
LFBGA
C14
D14
C13
C15
D13
A13
A15
E13
B12
A12
M2
M3
M4
M1
U9
Y7
N3
N2
N1
N4
P3
P2
P1
R3
N5
R2
R1
P4
R4
U1
U2
L4
T1
T2
T3
SCKE3
SCLK
nBLE0
nBLE1
nBLE2
nBLE3
nCAS
nRAS
DQM0
DQM1
DQM2
DQM3
PA0/
LCDVD16
PA1/
LCDVD17
PA2
PA3
PA4
PA5
PA6
PA7
PB0/UARTRX1
PB1/UARTTX3
PB2/UARTRX3
PB3/UARTCTS3
PB4/UARTDCD3
PB5/UARTDSR3
PB6/SWID/SMBD
PB7/SMBCLK
PC0/UARTTX1
PC1
PC2
PC3
PC4
PC5
PC6
SIGNAL
Clock Enable 3 for Synchronous Memory
Synchronous Memory Clock
Byte Lane Enable 0
Byte Lane Enable 1
Byte Lane Enable 2
Byte Lane Enable 3
Synchronous Memory Column Address Strobe
Synchronous Memory Row Address Strobe
Data Mask for Synchronous Memories
• GPIO Port A0
• LCD Data pin 16
• GPIO Port A1
• LCD Data pin 17
GPIO Port A[6:2]
• GPIO Port A7
• Boot Width Selection (See Table 6)
• GPIO Port B0
• UART1 Receive Data Input
• GPIO Port B1
• UART3 Transmit Data Out
• GPIO Port B2
• UART3 Receive Data In
• GPIO Port B3
• UART3 Clear to Send
• GPIO Port B4
• UART3 Data Carrier Detect
• GPIO Port B5
• UART3 Data Set Ready
• GPIO Port B6
• Single Wire Data
• Smart Battery Data
• GPIO Port B7
• Smart Battery Clock
• GPIO Port C0
• UART1 Transmit Data Output
GPIO Port C[5:1]
GPIO Port C6
Table 2. LH7A404 Functional Pin List (Cont’d)
DESCRIPTION
NXP Semiconductors
Depends on
PB3: Input
PB4: Input
PB5: Input
PB6: Input
PB7: Input
PC0: LOW
PCx: LOW
PC6: LOW
PA0: Input
PA1: Input
PAx: Input
PA7: Input
PB0: Input
PB1: Input
PB2: Input
MEDCHG
RESET
STATE
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
STATE
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
OUTPUT
DRIVE
12 mA
20 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
I/O NOTES
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
LH7A404
2
4
4
7