LH7A404N0F000B3;55 NXP Semiconductors, LH7A404N0F000B3;55 Datasheet - Page 63

IC ARM9 BLUESTREAK MCU 324LFBGA

LH7A404N0F000B3;55

Manufacturer Part Number
LH7A404N0F000B3;55
Description
IC ARM9 BLUESTREAK MCU 324LFBGA
Manufacturer
NXP Semiconductors
Series
BlueStreak ; LH7Ar
Datasheet

Specifications of LH7A404N0F000B3;55

Package / Case
324-LFBGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, Microwire, MMC, PS2, SmartCard, SPI, SSI, SSP, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
LH7A4
Core
ARM9TDMI
Data Bus Width
32 bit
Data Ram Size
80 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
64
Number Of Timers
3
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4304 - BOARD EVAL FOR LH7A404
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4335
935285069557
LH7A404N0F000B3
32-Bit System-on-Chip
Clock and State Controller
(CSC) Waveforms
coming out of Reset or Power-On. Table 13 gives the
timing parameters.
32.768 kHz oscillator is stable, and must be deasserted
at least two 1 Hz clock periods before the WAKEUP
signal is asserted. Once the 14.7456 MHz oscillator is
stable, the PLLs require 250 µs to lock.
Boot), the Wakeup pin must not be asserted for two 1
NOTE: *VDDC = VDDCmin
NOTE: *The timing relationship is specified as a cycle-based timing. Due to variations in crystal input clock jitter,
Preliminary data sheet
tOSC32 (32 kHz)
tOSC14 (14 MHz)
Figure 48 shows the behavior of the LH7A404 when
At Power-On, nPOR must be held LOW until the
On transition from Standby to Run (including a Cold
PARAMETER
power rail noise and I/O conditioning these timings will vary marginally. It is recommended that designers
WAKEUP
XTAL32
XTAL14
VDDC
nPOR
VDDCmin
32.768 kHz Oscillator Stabilization Time after Power On*
14.7456 MHz Oscillator Stabilization Time after WAKEUP
tOSC32
DESCRIPTION
Table 13. Reset AC Timing
Figure 48. PLL Start-up
NXP Semiconductors
tOSC14
Hz clock periods after assertion of nPOR to allow time
for sampling BATOK and nEXTPWR. The delay
prevents a false ‘battery good’ indication caused by
alkaline battery recovery that can immediately follow a
battery-low switch off.
nRESETOUT Timing Sequence
each of the three reset triggers (nPOR, nURESET, and
nPWRFL) in Figure 49 through Figure 51, and timing
values are presented in Table 14 through Table 16.
Timing for the nRESETOUT sequence is shown for
MIN. MAX.
550
2.5
UNIT
ms
ms
LH7A404
LH7A404-22
63

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