LPC3130FET180,551 NXP Semiconductors, LPC3130FET180,551 Datasheet - Page 23

• Manufacturer Part Number: LPC3130FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3130FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: LPC3000
• Device Core: ARM926EJ-S
• Device Core Size: 16/32Bit
• Frequency (max): 180MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 96KB
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/2.8/3.3/5V
• Operating Supply Voltage (max): 1.3/3.6V
• Operating Supply Voltage (min): 1/1.1/1.65/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 180
• Package Type: TFBGA
• Package: 180TFBGA
• Family Name: LPC3000
• Maximum Speed: 180 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4696; 935288013551; LPC3130FET180-S

NXP Semiconductors
LPC3130_3131
Preliminary data sheet
6.14 APB bridge
6.15 Clock Generation Unit (CGU)
The APB bridge is a bus bridge between the AMBA Advanced High-performance Bus
(AHB) and the ARM Peripheral Bus (APB) interface.
The module supports two different architectures:
The clock generation unit generates all clock signals in the system and controls the reset
signals for all modules. The structure of the CGU is shown in
generated by the CGU belongs to one of the domains. Each clock domain is fed by a
single base clock that originates from one of the available clock sources. Within a clock
domain, fractional dividers are available to divide the base clock to a lower frequency.
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•
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Supports all combinations of 32-bit masters and slaves (fully connected interconnect
matrix).
Round-robin priority mechanism for bus arbitration: all masters have the same priority
and get bus access in their natural order
Four devices on a master port (listed in their natural order for bus arbitration):
– DMA
– ARM926 instruction port
– ARM926 data port
– USB OTG
Devices on a slave port (some ports are shared between multiple devices):
– AHB to APB Bridge 0
– AHB to APB Bridge 1
– AHB to APB Bridge 2
– AHB to APB Bridge 3
– AHB to APB Bridge 4
– Interrupt Controller
– NAND flash controller
– MCI SD/SDIO
– USB 2.0 high-speed OTG
– 96 kB ISRAM
– 96 kB ISRAM (LPC3131 only)
– 128 kB ROM
– MPMC
Single-clock architecture, synchronous bridge. The same clock is used at the AHB
side and at the APB side of the bridge. The AHB-to-APB4 bridge uses this
architecture.
Dual-clock architecture, asynchronous bridge. Different clocks are used at the AHB
side and at the APB side of the bridge. The AHB-to-APB0, AHB-to-APB1,
AHB-to-APB2, and AHB-to-APB3 bridges use this architecture.
All information provided in this document is subject to legal disclaimers.
Rev. 1.04 — 27 May 2010
Low-cost, low-power ARM926EJ-S microcontrollers
LPC3130/3131
Figure
6. Each output clock
© NXP B.V. 2010. All rights reserved.
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