LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 57
LPC1343FBD48,151
Manufacturer Part Number
LPC1343FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
40
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4945
935289652151
935289652151
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Company:
Part Number:
LPC1343FBD48,151
Manufacturer:
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Quantity:
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UM10375
User manual
5.6.2 Interrupt Set-Enable Register 1
Table 63.
The ISER1 register allows enabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Disabling interrupts is done through the
ICER0 and ICER1 registers
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 enables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 64.
Bit
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
0
1
2
3
4
5
6
7
8
9
10
Name
ISE_PIO1_3
ISE_PIO1_4
ISE_PIO1_5
ISE_PIO1_6
ISE_PIO1_7
ISE_PIO1_8
ISE_PIO1_9
ISE_PIO1_10
ISE_PIO1_11
ISE_PIO2_0
ISE_PIO2_1
ISE_PIO2_2
ISE_PIO2_3
ISE_PIO2_4
ISE_PIO2_5
ISE_PIO2_6
ISE_PIO2_7
Name
ISE_PIO2_8
ISE_PIO2_9
ISE_PIO2_10
ISE_PIO2_11
ISE_PIO3_0
ISE_PIO3_1
ISE_PIO3_2
ISE_PIO3_3
ISE_I2C0
ISE_CT16B0
ISE_CT16B1
Interrupt Set-Enable Register 0 register (ISER0 - address 0xE000 E100) bit
description
Interrupt Set-Enable Register 1 register (ISER1 - address 0xE000 E104) bit
description
All information provided in this document is subject to legal disclaimers.
Description
PIO1_3 start logic input interrupt enable.
PIO1_4 start logic input interrupt enable.
PIO1_5 start logic input interrupt enable.
PIO1_6 start logic input interrupt enable.
PIO1_7 start logic input interrupt enable.
PIO1_8 start logic input interrupt enable.
PIO1_9 start logic input interrupt enable.
PIO1_10 start logic input interrupt enable.
PIO1_11 start logic input interrupt enable.
PIO2_0 start logic input interrupt enable.
PIO2_1 start logic input interrupt enable.
PIO2_2 start logic input interrupt enable.
PIO2_3 start logic input interrupt enable.
PIO2_4 start logic input interrupt enable.
PIO2_5 start logic input interrupt enable.
PIO2_6 start logic input interrupt enable.
PIO2_7 start logic input interrupt enable.
…continued
PIO2_11 start logic input interrupt enable.
Timer CT16B0 interrupt enable.
Timer CT16B1 interrupt enable.
Description
PIO0_0 start logic input interrupt enable.
PIO2_9 start logic input interrupt enable.
PIO2_10 start logic input interrupt enable.
PIO3_0 start logic input interrupt enable.
PIO3_0 start logic input interrupt enable.
PIO3_0 start logic input interrupt enable.
PIO3_0 start logic input interrupt enable.
I
2
Rev. 2 — 7 July 2010
C0 interrupt enable.
(Section 5.6.3
and
Chapter 5: LPC13xx Interrupt controller
Section
5.6.4).
UM10375
© NXP B.V. 2010. All rights reserved.
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