LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 203

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
12.10 I
UM10375
User manual
2
C implementation and operation
12.9.4 Slave Transmitter mode
mode. After the address and direction bit have been received, the SI bit is set and a valid
status code can be read from the Status register (I2STAT). Refer to
status codes and actions.
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I
operate as a master and as a slave. In the slave mode, the I
slave address and the General Call address. If one of these addresses is detected, an
interrupt is requested. When the microcontrollers wishes to become the bus master, the
hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I
interface switches to the slave mode immediately and can detect its own slave address in
the same serial transfer.
Figure 27
describes the individual blocks.
Fig 25. Format of Slave Receiver mode
Fig 26. Format of Slave Transmitter mode
S
from Master to Slave
from Slave to Master
S
from Master to Slave
from Slave to Master
shows how the on-chip I
SLAVE ADDRESS
SLAVE ADDRESS
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
RW=0
RW=1
2
C-bus interface is implemented, and the following text
A
A
DATA
DATA
Chapter 12: LPC13xx I2C-bus controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Sr = Repeated START condition
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
n bytes data transmitted
n bytes data received
A
A
2
C hardware looks for its own
DATA
DATA
Table 230
UM10375
© NXP B.V. 2010. All rights reserved.
A/A
A
for the
2
C
2
205 of 333
C may
P/Sr
P