DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F6010-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601030IPF

TABLE 2:
© 2010 Microchip Technology Inc.
Operations
Note 1:
Operating
Controller
Interrupt
Memory
Module
Voltage
Sleep
Timer
PWM
PWM
PWM
Flash
Mode
I
PWM
CAN
PSV
2
V
PLL
PLL
PLL
QEI
I/O
I
C™
2
DD
C
Only those issues indicated in the last column apply to the current silicon revision.
Lock Status bit
Operations on
Debug Mode
Slave Mode
Sleep Mode
Generators
I
Multiplexed
Addressing
Dead Time
Generation
DD
Operation
SILICON ISSUE SUMMARY (CONTINUED)
Override
Override
30 MIPS
4x Mode
8x Mode
Interrupt
Feature
Port Pin
with IC1
Output
Output
SFRs
10-bit
Read
Current
—
—
—
Number
Item
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
The output override function of the PWM module, controlled by
the OVDCON register and the OSYNC bit (PWMCON2<1>),
produces unexpected results when OSYNC = 1.
Unexpected results may occur when the OSYNC bit
(PWMCON2<1>) is set.
Unexpected output results may occur if the motor control PWM
is operated in Complementary mode with dead time and the
duty cycle near 0% or 100%.
Read operations performed on CAN module Special Function
Registers (SFRs), may yield incorrect results at operation over
20 MIPS.
This release of silicon exhibits a current draw (I
approximately 370 mA during a Row Erase operation
performed on program Flash memory.
Applications operating off 5 volts V
ensure the V
The 4x PLL mode of operation may not function correctly for
certain input frequencies.
An interrupt occurring immediately after modifying the CPU
IPL, interrupt IPL, interrupt enable or interrupt flag may cause
an address error trap.
If 8x PLL mode is used, the input frequency range is 5 MHz-10
MHz instead of 4 MHz-10 MHz.
The Quadrature Encoder Interface (QEI) module does not
generate an interrupt in a particular overflow condition.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also
increase beyond the specifications listed in the device data
sheet.
The I
an I
PTMR does not continue counting down after halting code
execution in Debug mode.
The port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from
Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
2
C slave.
2
C module loses incoming data bytes when operating as
2
C module is configured for 10-bit addressing using
DD
remains between 4.75V and 5.5V.
Issue Summary
DD
at 30 MIPS should
2
DD
C devices, the
dsPIC30F6010
) of
DS80459D-page 3
Revisions
B1
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)