DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F6010-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601030IPF

dsPIC30F6010
9. Module: CPU
DS80459D-page 10
When interrupt nesting is enabled (or NSTDIS bit
(INTCON1<15>) is ‘0’), the following sequence of
events will lead to an address error trap:
1. REPEAT loop is active.
2. An interrupt is generated during the execution
3. The CPU executes the Interrupt Service
4. Within the ISR, when the CPU is executing the
of the REPEAT loop.
Routine (ISR) of the source causing the
interrupt.
first instruction cycle of the 3-cycle RETFIE
(Return from Interrupt) instruction, a second
interrupt is generated by a source with a higher
interrupt priority.
EXAMPLE 8:
EXAMPLE 9:
__T1Interrupt:
__T1Interrupt:
Work around
Processing of Interrupt Service Routines should
be disabled while the RETFIE instruction is being
executed. This may be accomplished in two
different ways:
1. Place a DISI instruction immediately before
2. Immediately prior to executing the RETFIE
Affected Silicon Revisions
PUSH
.......
BCLR
POP
DISI
RETFIE
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
B1
X
the RETFIE instruction in all Interrupt Service
Routines of interrupt sources that may be
interrupted by other higher priority interrupt
sources (with priority levels 1 through 6). This
is shown in Example 8 in the Timer1 ISR. In
this example, a DISI instruction inhibits level 1
through level 6 interrupts for 2 instruction
cycles, while the RETFIE instruction is
executed.
instruction, increase the CPU priority level by
modifying the IPL<2:0> bits (SR<7:5>) to ‘111’
as shown in Example 9. This will disable all
interrupts between priority levels 1 through 7.
B2
X
W0
IFS0, #T1IF
W0
#1
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
;Another interrupt occurs
;here and it is processed
;correctly
;Another interrupt occurs
;here and it is processed
;correctly
DISI BEFORE RETFIE
RAISE IPL BEFORE RETFIE
;Timer1 ISR
;This line optional
;This line optional
;Timer1 ISR
© 2010 Microchip Technology Inc.