ATMEGA128L-8AU Atmel, ATMEGA128L-8AU Datasheet - Page 266

• Manufacturer Part Number: ATMEGA128L-8AU
• Description: IC AVR MCU 128K 8MHZ 3V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: 2-Wire/JTAG/USART
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 53
• Interface: 2-Wire/JTAG/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Programmable Memory: 128K Bytes
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

266
ATmega128
Table 104. Boundary-scan Signals for the ADC (Continued)
Note:
If the ADC is not to be used during scan, the recommended input values from Table 104
should be used. The user is recommended not to use the Differential Gain stages dur-
ing scan. Switch-Cap based gain stages require fast operation and accurate timing
which is difficult to obtain when used in a scan chain. Details concerning operations of
the differential gain stage is therefore not provided.
The AVR ADC is based on the analog circuitry shown in Figure 131 with a successive
approximation algorithm implemented in the digital logic. When used in Boundary-scan,
the problem is usually to ensure that an applied analog voltage is measured within some
limits. This can easily be done without running a successive approximation algorithm:
apply the lower limit on the digital DAC[9:0] lines, make sure the output from the com-
parator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the
output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
When using the ADC, remember the following
•
•
•
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3
when the power supply is 5.0V and AREF is externally connected to V
Signal
Name
SCTEST
ST
VCCREN
The Port Pin for the ADC channel in use must be configured to be an input with pull-
up disabled to avoid signal contention.
In normal mode, a dummy conversion (consisting of 10 comparisons) is performed
when enabling the ADC. The user is advised to wait at least 200ns after enabling the
ADC before controlling/observing any ADC signal, or perform a dummy conversion
before using the first result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD
signal low (Sample mode).
Incorrect setting of the switches in Figure 131 will make signal contention and may dam-
age the part. There are several input choices to the S&H circuitry on the negative input of
the output comparator in Figure 131. Make sure only one path is selected from either one
ADC pin, Bandgap reference source, or Ground.
The lower limit is:
The upper limit is:
Direction
as Seen
from the
ADC
Input
Input
Input
Description
Switch-cap TEST
enable. Output from
x10 gain stage send
out to Port Pin having
ADC_4
Output of gain stages
will settle faster if this
signal is high first two
ACLK periods after
AMPEN goes high.
Selects Vcc as the
ACC reference
voltage.
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
⋅
⋅
⋅
⋅
⁄
⁄
Recommen-
ded Input
when not
in Use
=
=
0
0
0
291
323
=
=
0x123
0x143
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
CC
.
2467M–AVR–11/04
0
0
0