ATMEGA128L-8AU Atmel, ATMEGA128L-8AU Datasheet

Page 1

... Programmable I/O Lines – 64-lead TQFP and 64-pad MLF • Operating Voltages – 2.7 - 5.5V for ATmega128L – 4.5 - 5.5V for ATmega128 • Speed Grades – MHz for ATmega128L – MHz for ATmega128 ® 8-bit Microcontroller 8-bit Microcontroller with 128K Bytes In-System ...

Page 2

Pin Configurations Overview ATmega128 2 Figure 1. Pinout ATmega128 PEN 1 RXD0/(PDI) PE0 2 (TXD0/PDO) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (ICP3/INT7) PE7 9 (SS) PB0 10 (SCK) PB1 ...

Page 3

Block Diagram Figure 2. Block Diagram PF0 - PF7 VCC GND PORTF DRIVERS DATA REGISTER PORTF REG. PORTF AVCC ADC AGND AREF PROGRAM JTAG TAP COUNTER PROGRAM ON-CHIP DEBUG FLASH BOUNDARY- INSTRUCTION SCAN REGISTER PROGRAMMING PEN INSTRUCTION LOGIC DECODER CONTROL ...

Page 4

... Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...

Page 5

ATmega103 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) 2467M–AVR–11/04 The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128” describes ...

Page 6

Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) Port G (PG4..PG0) ATmega128 6 current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock ...

Page 7

RESET XTAL1 XTAL2 AVCC AREF PEN About Code Examples 2467M–AVR–11/04 current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves ...

Page 8

AVR CPU Core Introduction Architectural Overview ATmega128 8 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform ...

Page 9

ALU – Arithmetic Logic Unit Status Register 2467M–AVR–11/04 an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly ...

Page 10

General Purpose Register File ATmega128 10 The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is ...

Page 11

X-register, Y-register, and Z- register 2467M–AVR–11/04 General Purpose Working Registers Most of the instructions operating on the Register file have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register ...

Page 12

Stack Pointer RAM Page Z Select Register – RAMPZ ATmega128 12 The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis- ter always ...

Page 13

Instruction Execution Timing Reset and Interrupt Handling 2467M–AVR–11/04 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure ...

Page 14

ATmega128 14 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested inter- rupts. All enabled interrupts can then interrupt the ...

Page 15

Interrupt Response Time 2467M–AVR–11/04 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep; enter sleep, ...

Page 16

AVR ATmega128 Memories In-System Reprogrammable Flash Program Memory ATmega128 16 This section describes the different memories in the ATmega128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega128 features ...

Page 17

SRAM Data Memory 2467M–AVR–11/04 The ATmega128 supports two different configurations for the SRAM data memory as listed in Table 1. Table 1. Memory Configurations Configuration Internal SRAM Data Memory Normal mode ATmega103 Compatibility mode Figure 9 shows how the ATmega128 ...

Page 18

ATmega128 18 The five different addressing modes for the data memory cover: Direct, Indirect with Dis- placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers. The ...

Page 19

Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL 2467M–AVR–11/04 This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk ...

Page 20

EEPROM Data Register – EEDR EEPROM Control Register – EECR ATmega128 20 These are reserved bits and will always read as zero. When writing to this address loca- tion, write these bits to zero for compatibility with future devices. • ...

Page 21

Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a ...

Page 22

ATmega128 22 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter- rupts globally) so that no interrupts will occur during execution of ...

Page 23

EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption 2467M–AVR–11/04 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of ...

Page 24

I/O Memory External Memory Interface Overview ATmega128 24 Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD ...

Page 25

ATmega103 Compatibility Using the External Memory Interface 2467M–AVR–11/04 Figure 11. External Memory with Sector Select Memory Configuration A Internal memory Lower sector SRW01 SRW00 External Memory Upper sector (0-60K x 8) SRW11 SRW10 Note: ATmega128 in non ATmega103 compatibility mode: ...

Page 26

Address Latch Requirements ATmega128 26 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – ...

Page 27

Pull-up and Bus-keeper Timing 2467M–AVR–11/04 The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode recommended to dis- able the pull-ups by writing ...

Page 28

ATmega128 28 Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock (CLK ) CPU ALE A15:8 Prev. addr. DA7:0 Prev. data Address WR DA7:0 (XMBK = 0) Prev. data Address Prev. data ...

Page 29

XMEM Register Description MCU Control Register – MCUCR External Memory Control Register A – XMCRA 2467M–AVR–11/04 Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = System Clock (CLK ) CPU ALE A15:8 Prev. ...

Page 30

ATmega128 possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of ...

Page 31

External Memory Control Register B – XMCRB Using all Locations of External Memory Smaller than 64 KB 2467M–AVR–11/04 Bit XMBK – – Read/Write R Initial Value • Bit 7– XMBK: External Memory ...

Page 32

ATmega128 32 When the device is set in ATmega103 compatibility mode, the internal address space is 4,096 bytes. This implies that the first 4,096 bytes of the external memory can be accessed at addresses 0x8000 to 0x8FFF. To the Application ...

Page 33

Using all 64KB Locations of External Memory 2467M–AVR–11/04 Since the External Memory is mapped after the Internal Memory as shown in Figure 11, only 60KB of External Memory is available by default (address space 0x0000 to 0x10FF is reserved for ...

Page 34

System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O Flash Clock – clk FLASH ATmega128 34 Figure 18 presents the principal clock systems in the AVR and their distribution. ...

Page 35

Asynchronous Timer Clock – clk ASY ADC Clock – clk ADC Clock Sources Default Clock Source 2467M–AVR–11/04 The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain ...

Page 36

Crystal Oscillator ATmega128 36 XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz crystal or a ceramic resonator may ...

Page 37

Low-frequency Crystal Oscillator 2467M–AVR–11/04 Table 9. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1..0 Power-save 00 258 258 ...

Page 38

External RC Oscillator ATmega128 38 For timing insensitive applications, the External RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming ...

Page 39

... RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a frequency within ± the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “ ...

Page 40

External Clock ATmega128 40 zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used ...

Page 41

Timer/Counter Oscillator XTAL Divide Control Register – XDIV 2467M–AVR–11/04 For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a ...

Page 42

Power Management and Sleep Modes MCU Control Register – MCUCR ATmega128 42 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the ...

Page 43

Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode 2467M–AVR–11/04 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- wire ...

Page 44

Standby Mode Extended Standby Mode Table 18. Active Clock Domains and Wake Up Sources in the Different Sleep Modes Active Clock Domains Sleep Mode clk clk clk clk CPU FLASH IO Idle X ADC Noise Reduction Power- down Power- save ...

Page 45

Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins 2467M–AVR–11/04 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep ...

Page 46

JTAG Interface and On-chip Debug System ATmega128 46 If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, ...

Page 47

System Control and Reset Resetting the AVR Reset Sources 2467M–AVR–11/04 During Reset, all I/O registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be ...

Page 48

ATmega128 48 Figure 22. Reset Logic D Q PEN L Q Pull-up Resistor Power-On Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE RESET FILTER JTAG Reset Watchdog Register Timer Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] Table 19. Reset Characteristics Symbol Parameter ...

Page 49

... This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega128L and BODLEVEL=0 for ATmega128. BODLEVEL=1 is not applicable for ATmega128. A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 19 ...

Page 50

Brown-out Detection ATmega128 50 Figure 25. External Reset During Operation CC ATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD ...

Page 51

Watchdog Reset MCU Control and Status Register – MCUCSR 2467M–AVR–11/04 When the Watchdog times out, it will generate a short reset pulse cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting ...

Page 52

Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer ATmega128 52 ATmega128 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator ...

Page 53

Watchdog Timer Control Register – WDTCR 2467M–AVR–11/04 Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON. M103C WDTON Unprogrammed Unprogrammed Unprogrammed Programmed Programmed Unprogrammed Programmed Programmed Figure 28. Watchdog Timer WATCHDOG OSCILLATOR Bit 7 ...

Page 54

ATmega128 the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four ...

Page 55

Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 2467M–AVR–11/04 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled ...

Page 56

Safety Level 2 ATmega128 56 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the ...

Page 57

Interrupts Interrupt Vectors in ATmega128 2467M–AVR–11/04 This section describes the specifics of the interrupt handling as performed in ATmega128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 23. Reset ...

Page 58

ATmega128 58 Table 23. Reset and Interrupt Vectors (Continued) Vector Program (2) No. Address Source (3) 31 $003C USART1, RX (3) 32 $003E USART1, UDRE (3) 33 $0040 USART1, TX (3) 34 $0042 TWI (3) 35 $0044 SPM READY Notes: ...

Page 59

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128 is: Address LabelsCode $0000 jmp RESET $0002 jmp EXT_INT0 $0004 jmp EXT_INT1 $0006 jmp EXT_INT2 $0008 jmp EXT_INT3 $000A jmp EXT_INT4 $000C jmp ...

Page 60

ATmega128 60 ... ... ... ... When the BOOTRST fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general ...

Page 61

Moving Interrupts Between Application and Boot Space MCU Control Register – MCUCR 2467M–AVR–11/04 $F049 out SPL,r16 $F04A sei $F04B <instr> xxx The General Interrupt Control Register controls the placement of the interrupt vector table. Bit SRE SRW10 ...

Page 62

ATmega128 62 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when ...

Page 63

I/O Ports Introduction 2467M–AVR–11/04 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin ...

Page 64

Ports as General Digital I/O Configuring the Pin ATmega128 64 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O port pin, here generically called Pxn. (1) Figure 30. General Digital ...

Page 65

Reading the Pin Value 2467M–AVR–11/04 When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. ...

Page 66

ATmega128 66 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region ...

Page 67

Digital Input Enable and Sleep Modes 2467M–AVR–11/04 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...

Page 68

Unconnected pins Alternate Port Functions ATmega128 68 If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described ...

Page 69

Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 33 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table ...

Page 70

Special Function IO Register – SFIOR Alternate Functions of Port A ATmega128 70 Bit TSM – – Read/Write R Initial Value • Bit 2 – PUD: Pull-up disable When this bit is ...

Page 71

Alternate Functions of Port B 2467M–AVR–11/04 Table 29. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AD3 PA2/AD2 PUOE SRE SRE PUOV ~(WR | ADA) • ~(WR | ADA) • PORTA3 • PUD PORTA2 • PUD DDOE SRE SRE ...

Page 72

ATmega128 72 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The ...

Page 73

Table 31. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/OC2/OC1C PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE OC2/OC1C ENABLE (1) PVOV OC2/OC1C DIEOE 0 DIEOV 0 DI – AIO – Note: 1. See “Output Compare ...

Page 74

Alternate Functions of Port C ATmega128 74 In ATmega103 compatibility mode, Port C is output only. The ATmega128 is by default shipped in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC ...

Page 75

Alternate Functions of Port D 2467M–AVR–11/04 Table 35. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PC3/A11 PC2/A10 PUOE SRE • (XMM<5) SRE • (XMM<6) PUOV 0 0 DDOE SRE • (XMM<5) SRE • (XMM<6) DDOV 1 1 PVOE ...

Page 76

ATmega128 76 • ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin for Timer/Counter1. • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 ...

Page 77

Table 37. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T2 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV INPUT AIO – Table 38. Overriding Signals for Alternate Functions ...

Page 78

Alternate Functions of Port E ATmega128 78 The Port E pins with alternate functions are shown in Table 39. Table 39. Port E Pins Alternate Functions Port Pin Alternate Function (1) PE7 INT7/ICP3 (External Interrupt 7 Input or Timer/Counter3 Input ...

Page 79

OC3A, Output Compare Match A output: The PE3 pin can serve as an External output for the Timer/Counter3 Output Compare A. The pin has to be configured as an output (DDE3 set “one”) to serve this function. The OC3A ...

Page 80

Alternate Functions of Port F ATmega128 80 Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Signal Name PE3/AIN1/OC3A PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE OC3B ENABLE PVOV OC3B DIEOE 0 DIEOV AIO AIN1 ...

Page 81

ADC5, Analog to Digital Converter, Channel 5 TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. ...

Page 82

Alternate Functions of Port G ATmega128 82 In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and Port G cannot be used as General Digital Port Pins. The alternate pin configura- tion is as follows: ...

Page 83

Table 47. Overriding Signals for Alternate Functions in PG0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega128 PG0/WR SRE 0 SRE 1 SRE – – 83 ...

Page 84

Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B ...

Page 85

Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE ...

Page 86

Port F Data Direction Register – DDRF Port F Input Pins Address – PINF Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING ATmega128 86 Bit ...

Page 87

External Interrupts External Interrupt Control Register A – EICRA 2467M–AVR–11/04 The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature pro- vides ...

Page 88

External Interrupt Control Register B – EICRB ATmega128 88 Table 48. Interrupt Sense Control ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request Reserved 1 0 The falling edge of INTn generates asynchronously ...

Page 89

External Interrupt Mask Register – EIMSK External Interrupt Flag Register – EIFR 2467M–AVR–11/04 Bit INT7 INT6 INT5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 – INT7 – INT0: External Interrupt Request 7 ...

Page 90

Timer/Counter0 with PWM and Asynchronous Operation Overview Registers ATmega128 90 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase ...

Page 91

Definitions Timer/Counter Clock Sources Counter Unit 2467M–AVR–11/04 operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decre- ment) its value. The Timer/Counter is inactive when ...

Page 92

Output Compare Unit ATmega128 92 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk Timer/Counter clock. T0 top Signalizes that TCNT0 has reached ...

Page 93

Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit 2467M–AVR–11/04 Figure 36. Output Compare Unit, Block Diagram OCRn top bottom Waveform Generator FOCn The OCR0 Register is double buffered when using any of the Pulse ...

Page 94

Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega128 94 The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value ...

Page 95

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2467M–AVR–11/04 A change of the COM01:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be ...

Page 96

Fast PWM Mode ATmega128 96 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP ...

Page 97

Figure 39. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter overflow flag ( interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the ...

Page 98

Phase Correct PWM Mode ATmega128 98 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly ...

Page 99

Timer/Counter Timing Diagrams 2467M–AVR–11/04 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The N variable represents the prescale factor (1, 8, ...

Page 100

ATmega128 100 Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, ...

Page 101

Timer/Counter Register Description Timer/Counter Control Register – TCCR0 2467M–AVR–11/04 Figure 44. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn ...

Page 102

ATmega128 102 Table 52. Waveform Generation Mode Bit Description (1) (1) WGM01 WGM00 Timer/Counter Mode (CTC0) (PWM0) Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Note: ...

Page 103

Timer/Counter Register – TCNT0 Output Compare Register – OCR0 2467M–AVR–11/04 Table 55. Compare Output Mode, Phase Correct PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected Reserved 1 0 Clear OC0 on compare match when ...

Page 104

Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter0 ATmega128 104 Bit – – – Read/Write Initial Value • Bit 3 – AS0: Asynchronous Timer/Counter0 When ...

Page 105

The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main clock frequency must be more than four times the ...

Page 106

Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega128 106 read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode ...

Page 107

Timer/Counter Prescaler Special Function IO Register – SFIOR 2467M–AVR–11/04 Figure 45. Prescaler for Timer/Counter0 clk clk I/O T0S Clear TOSC1 AS0 PSR0 CS00 CS01 CS02 The clock source for Timer/Counter0 is named clk main system clock clk . By setting ...

Page 108

ATmega128 108 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the ...

Page 109

Timer/Counter (Timer/Counter1 and Timer/Counter3) Restrictions in ATmega103 Compatibility Mode Overview 2467M–AVR–11/04 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.,Allows 16-bit ...

Page 110

Registers ATmega128 110 Figure 46. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTx = OCRxA = OCRxB = OCRxC ICRx TCCRxA Note: Refer to Figure 1 on page 2, Table 30 on page 71, and Table 39 on page ...

Page 111

Definitions Compatibility 2467M–AVR–11/04 generator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B/C). See “Output Compare Units” on page 118.. The compare match event will also set the compare match flag (OCFnA/B/C) which can be ...

Page 112

Accessing 16-bit Registers ATmega128 112 The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. ...

Page 113

It is important to notice that accessing 16-bit registers are atomic operations inter- rupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any ...

Page 114

Reusing the Temporary High Byte Register ATmega128 114 The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. ...

Page 115

Timer/Counter Clock Sources Counter Unit 2467M–AVR–11/04 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in ...

Page 116

Input Capture Unit ATmega128 116 TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of ...

Page 117

Input Capture Pin Source Noise Canceler Using the Input Capture Unit 2467M–AVR–11/04 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low ...

Page 118

Output Compare Units ATmega128 118 (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used). The ...

Page 119

Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit 2467M–AVR–11/04 The OCRnx Register is double buffered when using any of the twelve Pulse Width Mod- ulation (PWM) modes. For the normal and Clear Timer on ...

Page 120

Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega128 120 The Compare Output mode (COMnx1:0) bits have two functions. The waveform genera- tor uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare ...

Page 121

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2467M–AVR–11/04 A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be ...

Page 122

Fast PWM Mode ATmega128 122 Figure 51. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 1 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according ...

Page 123

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit ...

Page 124

Phase Correct PWM Mode ATmega128 124 ing at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written ...

Page 125

OCRnA set to 0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: R PCPWM In phase correct PWM mode the counter ...

Page 126

Phase and Frequency Correct PWM Mode ATmega128 126 at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall- ing slope is determined by the previous TOP value, while the length of the ...

Page 127

R PFCPWM In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached ...

Page 128

Timer/Counter Timing Diagrams ATmega128 128 As Figure 54 shows the output generated is, in contrast to the phase correct mode, sym- metrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the ...

Page 129

Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 56 shows the same timing data, but with the prescaler enabled. Figure 56. Timer/Counter Timing ...

Page 130

ATmega128 130 Figure 57. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx ...

Page 131

Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A 2467M–AVR–11/04 Bit COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value Bit COM3A1 COM3A0 COM3B1 ...

Page 132

ATmega128 132 Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode Table 59. Compare Output Mode, Fast PWM COMnA1/COMnB1/ COMnA0/COMnB0/ COMnC0 COMnC0 Note: ...

Page 133

Table 61. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...

Page 134

Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B ATmega128 134 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value Bit ICNC3 ICES3 – Read/Write R/W R/W ...

Page 135

Timer/Counter1 Control Register C – TCCR1C Timer/Counter3 Control Register C – TCCR3C 2467M–AVR–11/04 Table 62. Clock Select Bit Description CSn2 CSn1 CSn0 Description clock source. (Timer/Counter stopped clk /1 (No prescaling I/O 0 ...

Page 136

Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter3 – TCNT3H and TCNT3L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Output Compare Register 1 C – OCR1CH and OCR1CL Output Compare Register ...

Page 137

Output Compare Register 3 B – OCR3BH and OCR3BL Output Compare Register 3 C – OCR3CH and OCR3CL Input Capture Register 1 – ICR1H and ICR1L Input Capture Register 3 – ICR3H and ICR3L 2467M–AVR–11/04 Bit Read/Write ...

Page 138

Timer/Counter Interrupt Mask Register – TIMSK Extended Timer/Counter Interrupt Mask Register – ETIMSK ATmega128 138 Bit OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value Note: This register contains interrupt control bits for several ...

Page 139

Timer/Counter Interrupt Flag Register – TIFR 2467M–AVR–11/04 corresponding interrupt vector (see “Interrupts” on page 57) is executed when the OCF3A flag, located in ETIFR, is set. • Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable When this ...

Page 140

Extended Timer/Counter Interrupt Flag Register – ETIFR ATmega128 140 Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed. Alternatively, OCF1B can ...

Page 141

This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Out- put Compare Register C (OCR3C). Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag. OCF3C is automatically ...

Page 142

Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega128 142 Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler mod- ule, but the Timer/Counters can have different prescaler settings. The description below applies to all of ...

Page 143

Special Function IO Register – SFIOR 2467M–AVR–11/04 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system ...

Page 144

Timer/Counter2 with PWM Overview Registers ATmega128 144 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width ...

Page 145

Definitions Timer/Counter Clock Sources Counter Unit 2467M–AVR–11/04 inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T2 The double buffered Output Compare Register (OCR2) is compared with ...

Page 146

Output Compare Unit ATmega128 146 clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock, referred to as clk Tn top Signalize that TCNT2 has reached maximum value. bottom Signalize that TCNT2 has reached minimum value (zero). Depending of ...

Page 147

Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit 2467M–AVR–11/04 Figure 63. Output Compare Unit, Block Diagram OCRn = top bottom Waveform Generator FOCn WGMn1:0 The OCR2 Register is double buffered when using any of ...

Page 148

Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega128 148 put Compare (FOC2) strobe bits in normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are ...

Page 149

Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2467M–AVR–11/04 A change of the COM21:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be ...

Page 150

Fast PWM Mode ATmega128 150 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP ...

Page 151

Figure 66. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If the interrupt is enabled, the interrupt handler routine can be used ...

Page 152

Phase Correct PWM Mode ATmega128 152 The phase correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly ...

Page 153

OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The N variable represents the prescale factor (1, 8, 64, 256, or ...

Page 154

Timer/Counter Timing Diagrams ATmega128 154 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 68 contains timing ...

Page 155

Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ...

Page 156

Timer/Counter Register Description Timer/Counter Control Register – TCCR2 ATmega128 156 Bit FOC2 WGM20 COM21 Read/Write W R/W R/W Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only ...

Page 157

Table 65. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected Toggle OC2 on compare match 1 0 Clear OC2 on compare match 1 1 Set OC2 on compare match Table ...

Page 158

Timer/Counter Register – TCNT2 Output Compare Register – OCR2 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega128 158 Table 68. Clock Select Bit Description CS22 CS21 CS20 Description clk /1024 (From prescaler) ...

Page 159

Read/Write R/W R/W R/W Initial Value • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output ...

Page 160

Output Compare Modulator (OCM1C2) Overview Description ATmega128 160 The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output ...

Page 161

Timing Example 2467M–AVR–11/04 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. Figure ...

Page 162

Serial Peripheral Interface – SPI ATmega128 162 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega128 and peripheral devices or between several AVR devices. The ATmega128 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data ...

Page 163

When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register ...

Page 164

ATmega128 164 Note: 1. See “Alternate Functions of Port B” on page 71 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as ...

Page 165

The following code examples show how to initialize the SPI as a slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable ...

Page 166

SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega128 166 When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and ...

Page 167

SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high ...

Page 168

SPI Status Register – SPSR SPI Data Register – SPDR ATmega128 168 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer ...

Page 169

Data Modes 2467M–AVR–11/04 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 77 and Figure 78. Data ...

Page 170

USART Dual USART Overview ATmega128 170 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or ...

Page 171

Figure 79. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: Refer to Figure 1 on page 2, Table 36 on page 75, and Table 39 on page 78 ...

Page 172

AVR USART vs. AVR UART – Compatibility Clock Generation ATmega128 172 The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • ...

Page 173

Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) 2467M–AVR–11/04 Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock ...

Page 174

External Clock Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock ATmega128 174 receiver will in this case only use half the number of samples (reduced from 16 to ...

Page 175

Frame Formats Parity Bit Calculation 2467M–AVR–11/04 A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of ...

Page 176

USART Initialization ATmega128 176 If used, the parity bit is located between the last data bit and first stop bit of a serial frame. The USART has to be initialized before any communication can take place. The initial- ization process ...

Page 177

Data Transmission – The USART Transmitter Sending Frames with Data Bit 2467M–AVR–11/04 More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a fixed ...

Page 178

ATmega128 178 The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the data register empty interrupt is utilized, the interrupt routine writes the ...

Page 179

Sending Frames with 9 Data Bit Transmitter Flags and Interrupts 2467M–AVR–11/04 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written ...

Page 180

Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega128 180 When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register ...

Page 181

The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will ...

Page 182

Receiving Frames with 9 Data Bits ATmega128 182 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, ...

Page 183

Receive Compete Flag and Interrupt Receiver Error Flags 2467M–AVR–11/04 Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must ...

Page 184

Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception ATmega128 184 The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is ...

Page 185

Asynchronous Clock Recovery Asynchronous Data Recovery 2467M–AVR–11/04 The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig- ure 83 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times ...

Page 186

Asynchronous Operational Range ATmega128 186 the first stop bit of a frame. Figure 85 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 85. Stop Bit Sampling and ...

Page 187

Multi-processor Communication Mode 2467M–AVR–11/04 Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit slow 5 93,20 6 94,12 7 94,81 8 95,36 9 95,81 10 96,17 Table 76. ...

Page 188

Using MPCM ATmega128 188 data frames. When the frame type bit (the first stop or the 9th bit) is one, the frame con- tains an address. When the frame type bit is zero the frame is a data frame. The ...

Page 189

USART Register Description USARTn I/O Data Register – UDRn USART Control and Status Register A – UCSRnA 2467M–AVR–11/04 Bit Read/Write R/W R/W R/W Initial Value The USARTn Transmit Data Buffer Register and USARTn Receive ...

Page 190

USARTn Control and Status Register B – UCSRnB ATmega128 190 • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e. when the first stop ...

Page 191

USART Control and Status Register C – UCSRnC 2467M–AVR–11/04 Writing this bit to one enables the USARTn Receiver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating ...

Page 192

ATmega128 192 Table 78. UPMn Bits Settings UPMn1 UPMn0 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The ...

Page 193

USART Baud Rate Registers – UBRRnL and UBRRnH 2467M–AVR–11/04 Bit – – – Read/Write R/W R/W R/W Initial Value UBRRnH is not available in mega103 ...

Page 194

Examples of Baud Rate Setting Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% ...

Page 195

Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 3.6864 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 0.0% ...

Page 196

Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 ...

Page 197

Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 16.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 0.6% ...

Page 198

Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology Electrical Interconnection ATmega128 198 • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as ...

Page 199

Data Transfer and Frame Format Transferring Bits START and STOP Conditions 2467M–AVR–11/04 devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line high. Note that all ...

Page 200

Address Packet Format Data Packet Format ATmega128 200 All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a ...