AT91SAM7XC256B-CU Atmel, AT91SAM7XC256B-CU Datasheet - Page 17
![MCU ARM 256K HS FLASH 100-TFBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
AT91SAM7XC256B-CU
Manufacturer Part Number
AT91SAM7XC256B-CU
Description
MCU ARM 256K HS FLASH 100-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7XC128B-CU.pdf
(47 pages)
Specifications of AT91SAM7XC256B-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
91S
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, Ethernet, SPI, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
62
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
7.4
6209DS–ATARM–17-Feb-09
Peripheral DMA Controller
• Embedded Flash Controller
• Handles data transfer between peripherals and memories
• Seventeen channels
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirements
– Embedded Flash interface, up to three programmable wait states
– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– Two for the Advanced Encryption Standard 128-bit accelerator
– Two for the Triple Data Encryption Standard 128-bit accelerator
– One for the Analog-to-digital Converter
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
wait states
AT91SAM7XC512/256/128 Preliminary
17