ATMEGA1281V-8MU Atmel, ATMEGA1281V-8MU Datasheet - Page 166

• Manufacturer Part Number: ATMEGA1281V-8MU
• Description: IC MCU AVR 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1281V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.33 TIMSK1 – Timer/Counter 1 Interrupt Mask Register
16.11.34 TIMSK3 – Timer/Counter 3 Interrupt Mask Register
16.11.35 TIMSK4 – Timer/Counter 4 Interrupt Mask Register
16.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register
2549M–AVR–09/10
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
Bit
(0x6F)
Read/Write
Initial Value
Bit
(0x71)
Read/Write
Initial Value
Bit
(0x72)
Read/Write
Initial Value
Bit
(0x73)
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 138.
“Interrupts” on page
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
“Interrupts” on page
“Interrupts” on page
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ATmega640/1280/1281/2560/2561
105) is executed when the ICFn Flag, located in TIFRn, is set.
ICIE1
ICIE3
ICIE4
ICIE5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
105) is executed when the OCFnC Flag, located in
105) is executed when the OCFnB Flag, located in
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCIE1C
OCIE3C
OCIE4C
OCIE5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCIE1B
OCIE3B
OCIE4B
OCIE5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE1A
OCIE3A
OCIE4A
OCIE5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOIE1
TOIE3
TOIE4
TOIE5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIMSK1
TIMSK3
TIMSK4
TIMSK5
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