ATMEGA1281V-8MU Atmel, ATMEGA1281V-8MU Datasheet - Page 159

• Manufacturer Part Number: ATMEGA1281V-8MU
• Description: IC MCU AVR 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1281V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. For more information on the different
modes, see
Table 16-3.
Table 16-4
PWM mode.
Table 16-4.
Note:
COMnA1
COMnB1
COMnC1
COMnA1
COMnB1
COMnC1
0
0
1
1
0
0
1
1
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at BOTTOM.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
“Modes of Operation” on page
COMnA0
COMnB0
COMnC0
COMnA0
COMnB0
COMnC0
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
0
1
0
1
0
1
0
1
disconnected (normal port operation). For all other WGM1 settings, normal
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C
See “Fast PWM Mode” on page 150.
Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at
Set OCnA/OCnB/OCnC on compare match, clear OCnA/OCnB/OCnC at
Clear OCnA/OCnB/OCnC on compare match (set output to low level).
Set OCnA/OCnB/OCnC on compare match (set output to high level).
ATmega640/1280/1281/2560/2561
Table 16-2 on page
Normal port operation, OCnA/OCnB/OCnC disconnected.
Normal port operation, OCnA/OCnB/OCnC disconnected.
port operation, OC1A/OC1B/OC1C disconnected.
Toggle OCnA/OCnB/OCnC on compare match.
148.
BOTTOM (non-inverting mode).
BOTTOM (inverting mode).
148. Modes of operation supported by the
Description
Description
for more details.
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