ATMEGA1281V-8MU Atmel, ATMEGA1281V-8MU Datasheet - Page 113

• Manufacturer Part Number: ATMEGA1281V-8MU
• Description: IC MCU AVR 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1281V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2
14.2.1
2549M–AVR–09/10
Register Description
EICRA – External Interrupt Control Register A
Figure 14-1. Normal pin change interrupt.
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in
on page 114
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an
interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt
Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt
flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis-
ter before the interrupt is re-enabled.
PCINT(0)
Bit
(0x69)
Read/Write
Initial Value
pcint_setflag
pcint_in_(n)
clk
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCIF
will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
LE
clk
ISC31
R/W
7
0
pin_lat
D
Q
ISC30
R/W
pin_sync
PCINT(0) in PCMSK(x)
6
0
ATmega640/1280/1281/2560/2561
ISC21
pcint_in_(0)
R/W
5
0
Table 14-1 on page
ISC20
R/W
4
0
0
x
clk
ISC11
R/W
3
0
114. Edges on INT3:0 are registered
pcint_syn
ISC10
R/W
2
0
ISC01
pcint_setflag
R/W
1
0
ISC00
R/W
0
0
PCIF
Table 14-2
EICRA
113