PIC18F4585-I/ML Microchip Technology, PIC18F4585-I/ML Datasheet - Page 340

• Manufacturer Part Number: PIC18F4585-I/ML
• Description: IC MCU FLASH 24KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 3.25 KB
• On-chip Adc: 11 bit
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 0.88 mm
• Interface Type: I2C, SPI, EUSART
• Length: 8 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
23.13 Bit Timing Configuration
The Baud Rate Control registers
BRGCON2, BRGCON3) control the bit timing for the
CAN bus interface. These registers can only be
modified
devices are in Configuration mode.
23.13.1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of T
23.13.2
The PRSEG bits set the length of the propagation seg-
ment in terms of T
Phase Segment 1 in T
many times the RXCAN pin is sampled. Setting this bit
to a
at T
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
Information Processing Time (which is fixed at 2 T
the PIC18F2585/2680/4585/4680).
23.13.3
The PHSEG2<2:0> bits set the length (in T
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>
bits have no effect.
23.14 Error Detection
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
23.14.1
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
DS39625C-page 338
Q
‘
1
/2 before the sample point and once at the normal
’
causes the bus to be sampled three times: twice
Registers
‘
1
’
when
, then the length of Phase Segment 2 is
BRGCON1
BRGCON2
BRGCON3
CRC ERROR
Q
the
. The SEG1PH bits set the length of
Q
.
Q
PIC18F2585/2680/4585/4680
. The SAM bit controls how
(BRGCON1,
Q
) of Phase
Q
Preliminary
for
values of both counters can be read by the MCU. These
accordance with the CAN bus specification.
23.14.2
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowl-
edge error has occurred, an error frame is generated
and the message will have to be repeated.
23.14.3
If a node detects a dominant bit in one of the four
segments, including End-Of-Frame, interframe space,
Acknowledge delimiter or CRC delimiter, then a form
error has occurred and an error frame is generated.
The message is repeated.
23.14.4
A bit error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no bit error is
generated because normal arbitration is occurring.
23.14.5
lf, between the Start-Of-Frame and the CRC delimiter,
six consecutive bits with the same polarity are
detected, the bit stuffing rule has been violated. A stuff
bit error occurs and an error frame is generated. The
message is repeated.
23.14.6
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous
message is aborted and the frame is repeated as soon
as possible. Furthermore, each CAN node is in one of
the three error states: “error-active”, “error-passive” or
“bus-off”, according to the value of the internal error
counters. The error-active state is the usual state
where the bus node can transmit messages and
activate error frames (made of dominant bits) without
any restrictions. In the error-passive state, messages
and passive error frames (made of recessive bits) may
be transmitted. The bus-off state makes it temporarily
impossible for the station to participate in the bus
communication. During this state, messages can
neither be received nor transmitted.
23.14.7
The PIC18F2585/2680/4585/4680 devices contain two
error counters: the Receive Error Counter (RXERRCNT)
and the Transmit Error Counter (TXERRCNT). The
counters
are
ACKNOWLEDGE ERROR
FORM ERROR
BIT ERROR
STUFF BIT ERROR
ERROR STATES
ERROR MODES AND ERROR
COUNTERS
incremented
© 2007 Microchip Technology Inc.
or
decremented
in